Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design

Cui, Yijun; Gu, Chongyan; Wang, Chenghua; O’Neill, Máire; Liu, Weiqiang

doi:10.1109/access.2018.2839363

Cited by 26 publications

(14 citation statements)

References 20 publications

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“…Table 4 shows that the proposed XRRO PUF has better uniqueness compared with the conventional RO PUF [6] and the CRO PUF [7,20]. However, it is slightly worse compared with the RRO PUF [4]. The reliability of the RRO PUF is worse than for the proposed XRRO PUF.…”

Section: Results Comparison For Proposed Rpufsmentioning

confidence: 99%

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XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

Liu

Zhang

et al. 2019

ACM Trans. Embed. Comput. Syst.

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With the rapid development of the Internet of Things (IoT), security has attracted considerable interest. Conventional security solutions that have been proposed for the Internet based on classical cryptography cannot be applied to IoT nodes as they are typically resource-constrained. A physical unclonable function (PUF) is a hardware-based security primitive and can be used to generate a key online or uniquely identify an integrated circuit (IC) by extracting its internal random differences using so-called challenge-response pairs (CRPs). It is regarded as a promising low-cost solution for IoT security. A logic reconfigurable PUF (RPUF) is highly efficient in terms of hardware cost. This article first presents a new classification for RPUFs, namely circuitbased RPUF (C-RPUF) and algorithm-based RPUF (A-RPUF); two Exclusive OR (XOR)-based RPUF circuits (an XOR-based reconfigurable bistable ring PUF (XRBR PUF) and an XOR-based reconfigurable ring oscillator PUF (XRRO PUF)) are proposed. Both the XRBR and XRRO PUFs are implemented on Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The implementation results are compared with previous PUF designs and show good uniqueness and reliability. Compared to conventional PUF designs, the most significant advantage of the proposed designs is that they are highly efficient in terms of hardware cost. Moreover, the XRRO PUF is the most efficient design when compared with previous RPUFs. Also, both the proposed XRRO and XRBR PUFs require only 12.5% of the hardware resources of previous bitstable ring PUFs and reconfigurable RO PUFs, respectively, to generate a 1-bit response. This confirms that the proposed XRBR and XRRO PUFs are very efficient designs with good uniqueness and reliability. CCS Concepts: • Security and privacy → Security in hardware; Embedded systems security; • Hardware → Reconfigurable logic applications;

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Section: Results Comparison For Proposed Rpufsmentioning

confidence: 99%

“…Hence, it is known as a "weak" PUF [11] and is usually used as a key generator. There are also other memory-based PUF designs such as the butterfly PUF [15] and the tristate static random access memory (TSRAM) PUF [4].…”

Section: Traditional Puf Structuresmentioning

confidence: 99%

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

Liu

Zhang

et al. 2019

ACM Trans. Embed. Comput. Syst.

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“…Moreover, the hn-CRO PUF is a configurable strong PUF since it can generate sufficient CRPs. [15] 46.2% 49.97% Yes ReRAM PUF [16] 47.28% 49.85% No XBAR PUF [17] 49.5-50% 50% No TCRO PUF [5] 52 Gate per CRP bit RO PUF in [1] CRO1 PUF in [2] CRO2 PUF in [3] This work Fig. 8: Comparison of the cost efficiency for RO and CRO PUFs.…”

Section: B Puf Performancementioning

confidence: 93%

“…A typical CRO PUF is composed of switching components and delay components, where the switching components provide the reconfigurability to the PUF structure when the design is completed and deployed. The MUXs in [2]- [4] and the tristate gates in [5] act as the switching components and selects which delay unit is involved in the construction of the CRO PUF.…”

Section: Introductionmentioning

confidence: 99%

Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits

Cui

Wang

Liu

et al. 2020

IEEE Open J. Nanotechnol.

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Physical unclonable function (PUF) is a lightweight security primitive for energy constrained digital systems. As an enhanced design of conventional ring oscillator (RO) PUFs, configurable ring oscillator (CRO) PUFs improve the uniqueness and reliability compared with the conventional RO PUF designs. In typical CRO PUF designs, multiplexers (MUXs) are utilized as configurable components. In this paper, a hybrid nano-scale CRO (hn-CRO) PUF is proposed. The configurable components of the proposed hn-CRO PUF are implemented by RRAMs. The delay elements are based on CMOS inverters. Compared with traditional CRO PUF designs, the proposed hn-CRO PUF is cost-efficient in terms of circuit density and gate per challenge response pair (CRP) bit. To validate the proposed hn-CRO PUF, the Monte Carlo simulation results of a compact RRAM model under UMC 65nm technology are presented. The results show that the proposed hn-CRO PUF has a good uniqueness and low hardware consumption compared with the previous works.

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“…Cui proposed a fixed frequency CRO PUF based on the tristate inverters, which configures the delay unit by changing the delay elements in the delay unit [19] [20]. The tri-state matrix unit consists of an n × m CMOS tri-state gate array and…”

Section: B Security Analysis For Fixed Frequency Cro Pufmentioning

confidence: 99%

Theoretical Analysis of Configurable RO PUFs and Strategies to Enhance Security

Gao

Cui

et al. 2019

2019 IEEE International Workshop on Signal Processing Systems (SiPS)

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Compared to traditional ring oscillator PUF (RO PUF), configurable RO PUF (CRO PUF) greatly increases the number of challenge response pairs (CRPs) and improves hardware utilization. However, in the conventional CRO PUF design, when a path is selected by the challenge to generate a response, the circuit characteristic information constituting the CRO PUF, such as the delay information of the configurable unit, the transmission model, and etc., can also be leaked. Once the adversary monitors and masters this information, they can use this information to attack the CRO PUF circuits, such as modeling attacks. This paper establishes a theoretical model of CRO PUF and analyzes its unpredictability and security. Based on this model, a new mechanism to generate the proper challenges is proposed in this paper. In the proposed mechanism, the challenge is generated and utilized by a specific way, which can delay the feature leakage of the CRO PUF, thereby improving the security of the CRO PUF.

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Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design

Cited by 26 publications

References 20 publications

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

XOR-Based Low-Cost Reconfigurable PUFs for IoT Security

Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits

Theoretical Analysis of Configurable RO PUFs and Strategies to Enhance Security

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