UHF-1: a high speed complementary bipolar analog process on SOI

Davis, C.; Bajor, G.; Butler, J. E.; Crandell, T.L.; Delgado, J.A.; Jung, Tae-Hwa; Khajeh-Noori, Y.; Lomenick, B.; Milam, V.; Nicolay, H.C.; Richmond, Susan; Rivoli, T.

doi:10.1109/bipol.1992.274037

Cited by 25 publications

(1 citation statement)

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“…In order to reduce parasitics, various authors have reported devices fabricated on silicon-on-insulator (SOI) wafers and trench isolation. Bonded and etched back SOI (BESOI) wafers have found significant use in these processes [15], [18]- [21], [26], [35]- [37]. SOI wafers make the process simpler, i.e., no n-wells are needed for the PNP device isolation, and the device size and parasitic capacitances are reduced.…”

Section: Review Of Complementary Bipolar Technologiesmentioning

confidence: 99%

A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications

Bashir

Hebert²,

DeSantis³

et al. 2001

IEEE Trans. Electron Devices

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Abstract-Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP™ 1 ), which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies.

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