Fabrication of extremely thin silicon on insulator for fully-depleted CMOS applications

Semicond. Sci. Technol.

2006

This study shows the design and analysis of static NMOS gates composed of silicon nano-wire surrounding gate pull-down NMOSFETs (SGFETs) and p-type pull-up resistors as the primary building blocks to form high density circuits. The device geometry and doping concentration of NMOS transistors and p-type resistors are varied until the lowest noise margin and standby power dissipation are obtained for an inverter. The optimum NMOS transistor and p-type resistor configurations are subsequently used to build various NOR-type static logic gates including a full adder to evaluate the transient performance, power consumption and layout area of each gate. A power-saving technique that replaces the p-type pull-up resistor with a p-type MESFET is also investigated for large-scale logic strings. Simulation results indicate that the worst-case rise and fall delays for a full adder are 130 ps and 90 ps at no capacitive load, and increase by 27.5 ps and 10 ps per fan-out, respectively. The worst-case power dissipation for the same circuit is 186.4 µW. The full adder circuit occupies approximately a 25 µm 2 area if laid out conventionally and 36 µm 2 if laid out on a crossbar platform. Compared to same feature size conventional CMOS technologies, silicon nano-wire technology offers simplicity in interconnect routing and reduction in the layout area for similar circuit performance.

show abstract

Section: Inverter Standby Power Dissipationsupporting

confidence: 56%

Section: Device Design Criteriamentioning

confidence: 99%

Static NMOS circuits for crossbar architectures using silicon nano-wire technology

Semicond. Sci. Technol.

2006

show abstract

“…This step is followed by a 5 nm gate oxide growth at 975 • C for 30 min. Next, 100 nm PECVD oxide is deposited anisotropically to define the gatesource boundary [25]. Anisotropic PECVD oxide deposits vertically to the starting silicon substrate only but it does not attach wire walls, as shown in figure 6(b).…”

Section: Process Flowmentioning

confidence: 99%

The design and analysis of dynamic NMOSFET/PMESFET logic using silicon nano-wire technology

Semicond. Sci. Technol.

2006

A complete study including process flow, device design and circuit design issues is conducted to investigate the possibility of using surrounding gate NMOSFETs and PMESFETs for an area-efficient technology. Three-dimensional device simulations are performed to analyse the maximum current drive capacity and OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are conducted on the optimum transistor designs and non-ideal I -V characteristics of the processed NMOSFET and PMESFET were measured and compared against the ideal characteristics. Various differential dynamic circuits including full adder, 2-input AND (OR) and XOR gates are built to measure transient performance, power dissipation and layout area based on the selected FET designs.

show abstract

Exploratory study on power-efficient silicon nano-wire dynamic NMOSFET/PMESFET logic

IET Science, Measurement &Amp; Technology

2007