Static NMOS circuits for crossbar architectures using silicon nano-wire technology

Abstract

This study shows the design and analysis of static NMOS gates composed of silicon nano-wire surrounding gate pull-down NMOSFETs (SGFETs) and p-type pull-up resistors as the primary building blocks to form high density circuits. The device geometry and doping concentration of NMOS transistors and p-type resistors are varied until the lowest noise margin and standby power dissipation are obtained for an inverter. The optimum NMOS transistor and p-type resistor configurations are subsequently used to build various NOR-type static logic gates including a full adder to evaluate the transient performance, power consumption and layout area of each gate. A power-saving technique that replaces the p-type pull-up resistor with a p-type MESFET is also investigated for large-scale logic strings. Simulation results indicate that the worst-case rise and fall delays for a full adder are 130 ps and 90 ps at no capacitive load, and increase by 27.5 ps and 10 ps per fan-out, respectively. The worst-case power dissipation for the same circuit is 186.4 µW. The full adder circuit occupies approximately a 25 µm 2 area if laid out conventionally and 36 µm 2 if laid out on a crossbar platform. Compared to same feature size conventional CMOS technologies, silicon nano-wire technology offers simplicity in interconnect routing and reduction in the layout area for similar circuit performance.

III–V Nanowires: Synthesis, Property Manipulations, and Device Applications

“…Specifically, there is no power consumed at 0 V input as a result of the "OFF" state of the driver; on the other hand, at 5 V input, the output current is the saturation current of the load at 0 V gate bias (∼0.8 A). As such, the static power dissipation is estimated to be as low as ∼4 W, which is comparable to the lowest NW NMOS reported values and far lower than their planar counterparts [60,61].…”

Tunable Electronic Transport Properties of Metal‐Cluster‐Decorated III–V Nanowire Transistors

“…Specifically, there is no power consumed at 0 V input as a result of the “OFF” state of the driver; on the other hand, the output current at 5 V input is the saturation current of the load at 0 V gate bias (≈0.8 μA as shown in Figure S6, Supporting Information). As such, the static power dissipation is estimated to be as low as ≈4 μW, which is comparable to the lowest NW NMOS reported values and far lower than their planar counterparts 37, 38. Further performance enhancements can also be achieved with the optimized device geometry with a top‐gated structure for the smaller parasitic capacitance.…”