Two Methods of Rijndael Implementation in Reconfigurable Hardware

Abstract

This paper presents an evaluation of the Rijndael cipher, the Advanced Encryption Standard winner, from the viewpoint of its implementation in a Field Programmable Devices (FPD). Starting with an analysis of algorithm's general characteristics a general cipher structure is described. Two different methods of Rijndael algorithm mapping to FPD are analyzed and suitability of available FPD families is evaluated. Finally, results of proposed mapping implemented in Altera FLEX, ACEX and APEX FPD are presented and compared with the fastest known Xilinx FPGA implementation. Results obtained are significantly faster than that of other implementations known up to now. 1 There are several vendors of FPD. These vendors use different names for their FPD-e.g. Field Programmable Gate Arrays (FPGA) by Xilinx and Complex Programmable Logic Devices (CPLD) by Altera. FPD abbreviation is used as common name for all of them.

NanoCMOS-Molecular Realization of Rijndael

“…The way to estimate density, speed, and power consumption of CMOL circuits has been described in [13]. If we estimate the cell area A cell as 64(F CMOS ) 2 [12], [13] with logic depth equal to 28, the same implementation on CMOL FPGA with will result the total gate delay equal to 0.15 ns, the total area equal to 84 µm 2 and the area-delay product equal to 12.6 µm 2 ns. A computer program was written for finding a pseudo-optimum yieldoptimized gate placement.…”

“…Through three Advanced Encryption Standard (AES) conferences, Rijndael [1] was selected as AES in October 2000. After adoption of Rijndael, its VLSI realization was taken into consideration and nowadays it is integrated in many various embedded applications like Web Servers, ATMs, Fiber Distributed Data Interfaces (FDDIs), smart cards, cellular phones… Since 2000, several architectures for efficient VLSI realization of AES algorithm have been proposed and their performance evaluated using ASIC libraries and FPGAs [2], [3], [4], [5], [6], [7]. Further integration or speed-up of such circuits will not be easily possible in conventional manners.…”

High-speed VLSI architectures for the AES algorithm

“…The MixColumns transformation considers the four bytes in each column of the State as the coefficients of a polynomial over , and multiplies by modulo where (2) denotes the number " " in hexadecimal form, while the notation used later in this paper stands for " " in binary form. In matrix form, the MixColumns transformation can be expressed as (3) Finally, the AddRoundKey involves only bit-wise XOR operations.…”

“…Various architectures have been proposed for the implementation of the MixColumns/InvMixColumns transformation [3], [5], [7], [14], [15]. Applying substructure sharing both to the computation of a byte and between the computation of the four bytes in a column of the State, an efficient MixColumns implementation architecture can be derived.…”

An Efficient Design of Security Accelerator for IEEE 802.15.4 Wireless Senor Networks

“…Early AES designs were mostly straightforward implementations of various loop unrolled and pipelined architecture [2][3][4][5][6] with limited number of architectural optimizations, which resulted in poor resource utilization. Later FPGA implementations focused on better utilization of FPGA resources [7][8][9][10].…”