An Efficient Design of Security Accelerator for IEEE 802.15.4 Wireless Senor Networks

Abstract

Abstract-In this paper, we provide a low cost AES core for ZigBee devices which accelerates the computation of AES algorithms. Also, by embedding the AES core, we present an efficient architecture of security accelerator satisfying the IEEE 802.15.4 specifications. In our experiments, we observed that the AES core and the security accelerator use fewer logic gates and consume lower power than other architectures based on blockwide and folded ones.

Compact implementation of CCM and GCM modes of AES using DSP blocks

“…Table 2 compares our CCM and GCM implementations with other works in literature. As depicted, we have obtained a better balance between area and throughput that other works that followed a pipelined implementation [5] or did not exploit the embedded resources capabilities [2] [3]. The AES-GCM throughput is smaller than the AES-CCM due to the implementation of the bit serial multiplication instead of a digit-serial or parallel approach.…”

“…There are already some papers about the implementation of the 802.15.4 security suite, using the standard FPGA logic available [2] [3]. In this paper we have focused on exploring the reductions in area that can be achieved using the DSP blocks of the new FPGAs.…”

Leveraging the DSP48E1 block in lightweight cryptographic implementations

“…In this respect, Song et al presented a compact implementation of AES-CCM and a Content Address Memory (CAM) in order to store the Access Control List (ACL) described in the standard. The design was synthesized on an Altera Stratix I (EP1S10F) and had a power consumption of 29 mW at 3 MHz [29]. On the other hand, Hamalainen et al proposed another compact AES architecture implemented in the Altera Cyclone I (EP1C4F) board.…”

Extending the IEEE 802.15.4 Security Suite with a Compact Implementation of the NIST P-192/B-163 Elliptic Curves

“…Their implementation consumes 98.92 mW clocked at 50 MHz. On the other hand, Song et al utilized the Altera Stratix I FPGA [10]. They also relied on the AES folded architecture.…”