2004
DOI: 10.1109/tvlsi.2004.832943
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High-speed VLSI architectures for the AES algorithm

Abstract: Abstract-This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of subpipelining can be further explored. Furth… Show more

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Cited by 343 publications
(41 citation statements)
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“…After an initial addroundkey, a round function is applied to the data block (consisting of bytesub, shiftrows, mixcolumns and addroundkey transformation, respectively). It is performed iteratively (Nr times) depending on the key length [14].…”
Section: Fig 1: Aes Algorithm-encryption Structurementioning
confidence: 99%
“…After an initial addroundkey, a round function is applied to the data block (consisting of bytesub, shiftrows, mixcolumns and addroundkey transformation, respectively). It is performed iteratively (Nr times) depending on the key length [14].…”
Section: Fig 1: Aes Algorithm-encryption Structurementioning
confidence: 99%
“…The most common coefficient multiplication is {02}× operation, which is often called xtime function [1]. Different xtime block sharing strategies are proposed in [5,6,7,8,9,10,11,12,13,14].…”
Section: Introductionmentioning
confidence: 99%
“…However, they report the bare minimal focus on the architectural design of the different symmetric lightweight security ciphers. All the lightweight ciphers defined so far have only look-up table-based S-boxes, which have their own limitations in hardware [18][19][20][21][22][23][24][25].…”
Section: Introductionmentioning
confidence: 99%