Two level bulk preload branch prediction

Bonanno, James; Collura, Adam; Lipetz, Daniel; Mayer, U.; Prasky, B. R.; Saporito, Anthony

doi:10.1109/hpca.2013.6522308

Cited by 17 publications

(15 citation statements)

References 9 publications

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“…A BTB miss occurs when an entry for a predicted taken branch is not found in the BTB. Most server workloads used for this study (detailed in Section 4) require up to 16K BTB entries to fully capture all branches in their instruction working sets, while OLTP on Oracle benefits from even 32K entries, corroborating prior work [3,5,18]. The storage capacity requirement of a 32K-entry BTB is around 280KB (Section 4 details the cost).…”

Section: Conventional Instruction-supply Pathsupporting

confidence: 50%

“…For PhantomBTB, this latency is a function of NOC and LLC access delays, likely running into tens of cycles for a manycore CMP. In the case of bulk preload, this latency is in excess of 15 cycles [3].…”

Section: Conventional Instruction-supply Pathmentioning

confidence: 99%

“…In a similar vein, bulk preload [3] maintains per-core two-level BTBs and fetches a group of BTB entries that belong to a fixed-size code region (i.e., 64 consecutive instruction blocks) upon a miss in that region from the second level into the first level. Bulk preload fails to eliminate the first miss in every region, because the first miss is the prefetch trigger.…”

Section: Related Workmentioning

confidence: 99%

“…One approach, called PhantomBTB, uses tempo-ral correlation, packing several entries that missed consecutively in the first level into blocks that are stored in the LLC using predictor virtualization [5]. Another approach, called Bulk Preload and implemented in the IBM zEC12, moves a set of spatially correlated regions (4KB) between a dedicated 24K-entry second-level BTB structure and the first level [3].…”

Section: Conventional Instruction-supply Pathmentioning

confidence: 99%

“…A brute-force approach to improve frontend performance is larger L1-I caches (e.g., Cavium ThunderX) or multi-level branch target buffers (BTB) [3,5,31], which exacerbate the silicon overprovisioning and are limited in effectiveness. Streambased prefetchers to hide the latency of instruction fetches from lower levels of the cache hierarchy approach the performance of a perfect L1-I, but incur prohibitive storage costs due to storage-intensive controlflow metadata required to make predictions [14,15].…”

Section: Introductionmentioning

confidence: 99%

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Confluence

Kaynak¹,

Grot

Falsafi³

2015

Proceedings of the 48th International Symposium on Microarchitecture

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Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instructionsupply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching techniques aimed separately at L1-I and BTB, resulting in high metadata costs and/or only modest performance improvements due to the complex control-flow histories required to effectively fill the two components ahead of the core's fetch stream.This work makes the observation that the metadata for both the L1-I and BTB prefetchers require essentially identical information; the control-flow history. While the L1-I prefetcher necessitates the history at block granularity, the BTB requires knowledge of individual branches inside each block. To eliminate redundant metadata and multiple prefetchers, we introduce Confluence -a frontend design with unified metadata for prefetching into both L1-I and BTB, whose contents are synchronized. Confluence leverages a stream-based prefetcher to proactively fill both components ahead of the core's fetch stream. The prefetcher maintains the control-flow history at block granularity and for each instruction block brought into the L1-I, eagerly inserts the set of branch targets contained in the block into the BTB. Confluence provides 85% of the performance improvement provided by an ideal frontend (with a perfect L1-I and BTB) with 1% area overhead per core, while the highest-performance alternative delivers only 62% of the ideal performance improvement with a per-core area overhead of 8%.

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Section: Conventional Instruction-supply Pathsupporting

confidence: 50%

Section: Conventional Instruction-supply Pathmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Conventional Instruction-supply Pathmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Confluence

Kaynak¹,

Grot

Falsafi³

2015

Proceedings of the 48th International Symposium on Microarchitecture

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A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

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Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers. KEYWORDSdynamic branch predictor, hybrid BP, neural BP, perceptron predictorside BP, pipelining, predictor accuracy, review, side BP, speculative execution, two-level BP INTRODUCTIONControl-changing instructions such as branches add uncertainty in the execution of dependent instructions and thus lead to large performance loss in pipelined processors. To offset their overhead, accurate prediction of branch outcomes is vital. Since branch misprediction incurs high latency (eg, 14 to 25 cycles 1 ) and wastes energy due to execution of instructions on wrong-path, an improvement in BP* accuracy can boost performance and energy efficiency significantly. For example, experiments on real processors showed that reducing the branch mispredictions by half improved the processor performance by 13%. 2Effective design and management of BPs, however, presents several challenges. Design of BP involves a strict tradeoff between area, energy, accuracy, and latency. An increase in BP complexity for improving accuracy may make it infeasible for implementation or offset its performance benefit. For example, a 512 KB perceptron predictor may provide lower instruction-per-cycle than its 32 KB version, 3 and a 2-cycle fully accurate BP may provide lower instruction-per-cycle than a 1-cycle partially inaccurate BP. 4 Further, due to its high access frequency, BP becomes a thermal hot-spot, 5 and hence, reducing its dynamic and leakage energy is important. Clearly, intelligent techniques are required for resolving these issues.Further, recently, researchers have demonstrated two security vulnerabilities viz., "Meltdown" and "Spectre," which exploit speculative execution feature of modern CPUs. 6-8 For example, Spectre vulnerability works on the observation that the speculative execution due to a branch misprediction may leave side effects, which can reveal sensitive data to attackers, eg, if the memory accesses performed during speculative execution depends on sensitive data, the resulting state of the cache forms a side-channel through which the sensitive data can be leaked. These vulnerabilities affect nearly every modern CPU. While avoiding speculative execution (eg, disabling branch prediction) can mitigate these vulnerabilities, it leads to significant performance loss. In light of these vulnerabilities and associated tradeoffs, a deeper study of branch predictors is definitely required. Contributions:In this ...

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Boomerang: A Metadata-Free Architecture for Control Flow Delivery

Kumar

Huang

Grot

et al. 2017

2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Abstract-Contemporary server workloads feature massive instruction footprints stemming from deep, layered software stacks. The active instruction working set of the entire stack can easily reach into megabytes, resulting in frequent frontend stalls due to instruction cache misses and pipeline flushes due to branch target buffer (BTB) misses. While a number of techniques have been proposed to address these problems, every one of them requires dedicated metadata structures, translating into significant storage and complexity costs.In this paper, we ask the question whether it is possible to achieve high-performance control flow delivery without the metadata costs of prior techniques. We revisit a previously proposed approach of branch-predictor-directed prefetching, which leverages just the branch predictor and BTB to discover and prefetch the missing instruction cache blocks by exploring the program control flow ahead of the core front-end. Contrary to conventional wisdom, we find that this approach can be effective in covering instruction cache misses in modern CMPs with long LLC access latencies and multi-MB server binaries. Our first contribution lies in explaining the reasons for the efficacy of branch-predictor-directed prefetching. Our second contribution is in Boomerang, a metadata-free architecture for control flow delivery. Boomerang leverages a branch-predictordirected prefetcher to discover and prefill not only the instruction cache blocks, but also the missing BTB entries. Crucially, we demonstrate that the additional hardware cost required to identify and fill BTB misses is negligible. Our experimental evaluation shows that Boomerang matches the performance of the state-of-the-art control flow delivery scheme without the latter's high metadata and complexity overheads.

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Two level bulk preload branch prediction

Cited by 17 publications

References 9 publications

Confluence

Confluence

A survey of techniques for dynamic branch prediction

Boomerang: A Metadata-Free Architecture for Control Flow Delivery

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