Confluence

Abstract

Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instructionsupply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching techniques aimed separately at L1-I and BTB, resulting in high metadata costs and/or only modest performance improvements due to the complex control-flow histories required to effectively fill the two components ahead of the core's fetch stream.This work makes the observation that the metadata for both the L1-I and BTB prefetchers require essentially identical information; the control-flow history. While the L1-I prefetcher necessitates the history at block granularity, the BTB requires knowledge of individual branches inside each block. To eliminate redundant metadata and multiple prefetchers, we introduce Confluence -a frontend design with unified metadata for prefetching into both L1-I and BTB, whose contents are synchronized. Confluence leverages a stream-based prefetcher to proactively fill both components ahead of the core's fetch stream. The prefetcher maintains the control-flow history at block granularity and for each instruction block brought into the L1-I, eagerly inserts the set of branch targets contained in the block into the BTB. Confluence provides 85% of the performance improvement provided by an ideal frontend (with a perfect L1-I and BTB) with 1% area overhead per core, while the highest-performance alternative delivers only 62% of the ideal performance improvement with a per-core area overhead of 8%.

Enhancing Power Efficiency in Branch Target Buffer Design with a Two-Level Prediction Mechanism

“…With the increasing demands on BTB capacity as program loads grow, reducing power consumption in BTB design is becoming increasingly vital. Kaynak et al proposed the AirBTB, a basic block BTB design that employs a branch bitmap for each branch table entry, simplifying the identification of branch instructions within cache blocks [10]. Chang et al [21] proposed an energy-efficient BTB lookup scheme for embedded processors, emphasizing the filtering of sequential execution instructions to decrease BTB access.…”

“…Convention BTB 100% 0% Air-BTB [10] 26.4-61.5% 26.4-61.5% TG-BTB [12] 10.75-22.5% 67.55-89.25% FIL-BTB [26] 10-30% 70-90% The proposed scheme 3-14% 86-97%…”

“…However, the increased BTB capacity introduces more access latency, resulting in longer branch instruction prediction times and increase power consumption. Kaynak et al introduced a BTB structure called AirBTB [10], which closely resembles an L1 cache and effectively reduces branch mispredictions. Nevertheless, its BTB table entries, exceeding 130 bits, and a high number of entries lead to substantial access latency, negatively affecting branch prediction performance.…”

Shooting Down the Server Front-End Bottleneck

“…While highly effective, each prefetcher requires hundreds of kilobytes of metadata storage per core. Recent temporal streaming research has focused on lowering the storage costs [8,13,14]; however, even with optimizations, for a many-core CMP running several consolidated workloads, the total storage requirements can reach into megabytes.…”

“…Meanwhile, conditional branches are maintained in a separate smallcapacity BTB. By exploiting prior observations on control flow commonality in instruction and BTB working sets [14],…”