Boomerang: A Metadata-Free Architecture for Control Flow Delivery

Kumar, Rakesh; Huang, Cheng‐Chieh; Grot, Boris; Nagarajan, Vijay

doi:10.1109/hpca.2017.53

Cited by 38 publications

(18 citation statements)

References 23 publications

(34 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The main bottleneck of BTB-directed prefetchers is BTB misses [33,34]. To correctly go far ahead of the fetch stream, such a prefetcher needs to detect the branches and predict their target.…”

Section: Btb-directed Prefetchersmentioning

confidence: 99%

“…The branches' directions can be identified using a branch predictor. Kumar et al investigated the effect of these two components on BTB-directed instruction prefetching [34]. They showed that while the branch predictor's accuracy is not important, BTB misses can significantly limit BTB-directed prefetchers' efficiency.…”

Section: Btb-directed Prefetchersmentioning

confidence: 99%

“…Modeling the wrong-path fetches is important as they may pollute the cache hierarchy if they eventually become useless. Or they may become useful as observed in [34], and hence, lower the usefulness of a prefetcher. The evaluated prefetchers are triggered on instruction or block addresses touched in the wrong-path, which affects their behavior.…”

Section: Simulation Frameworkmentioning

confidence: 99%

“…The most common instruction prefetchers are sequential prefetchers that, upon activation, send prefetch requests for a few subsequent blocks [47,56]. While sequential prefetchers are used in commodity processors [25,42,46,47], prior work has shown that such prefetchers leave a significant fraction of instruction misses uncovered, and hence, there is a substantial opportunity for improvement [21,32,34].…”

Section: Introductionmentioning

confidence: 99%

“…However, the proposed prefetcher is impractical because of its high storage cost. Nonetheless, PIF motivated many researchers to develop effective and storage-efficient prefetchers [8,26,28,[32][33][34].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

MANA: Microarchitecting an Instruction Prefetcher

Ansari,

Golshan,

Lotfi-Kamran

et al. 2021

Preprint

View full text Add to dashboard Cite

Sciences (IPM), IranL1 instruction (L1-I) cache misses are a source of performance bottleneck. Sequential prefetchers are simple solutions to mitigate this problem; however, prior work has shown that these prefetchers leave considerable potentials uncovered. This observation has motivated many researchers to come up with more advanced instruction prefetchers. In 2011, Proactive Instruction Fetch (PIF) showed that a hardware prefetcher could effectively eliminate all of the instruction-cache misses. However, its enormous storage cost makes it an impractical solution. Consequently, reducing the storage cost was the main research focus in the instruction prefetching in the past decade.Several instruction prefetchers, including RDIP and Shotgun, were proposed to offer PIF-level performance with significantly lower storage overhead. However, our findings show that there is a considerable performance gap between these proposals and PIF. While these proposals use different mechanisms for instruction prefetching, the performance gap is largely not because of the mechanism, and instead, is due to not having sufficient storage. Prior proposals suffer from one or both of the following shortcomings: (1) a large number of metadata records to cover the potential, and (2) a high storage cost of each record. The first problem causes metadata-miss, and the second problem prohibits the prefetcher from storing enough records within reasonably-sized storage.In this paper, we make the case that the key to designing a powerful and cost-effective instruction prefetcher is choosing the right metadata record and microarchitecting the prefetcher to minimize the storage. We find that high spatial correlation among instruction accesses leads to compact, accurate, and minimal metadata records. We also show that chaining these records is an effective way to enable robust and timely prefetching. Based on the findings, we propose MANA, which offers PIF-level performance with 15.7× lower storage cost. MANA outperforms RDIP and Shotgun by 12.5 and 29%, respectively. We also evaluate a version of MANA with no storage overhead and show that it offers 98% of the peak performance benefits.CCS Concepts: • Computer systems organization → Architectures.

show abstract

Section: Btb-directed Prefetchersmentioning

confidence: 99%

Section: Btb-directed Prefetchersmentioning

confidence: 99%

Section: Simulation Frameworkmentioning

confidence: 99%