Two Dimensional Electrostrictive Field Effect Transistor (2D-EFET): A sub-60mV/decade Steep Slope Device with High ON current

Abstract

This article proposes a disruptive device concept which meets both low power and high performance criterion for post-CMOS computing and at the same time enables aggressive channel length scaling. This device, hereafter refer to as two-dimensional electrostrictive field effect transistor or 2D-EFET, allows sub-60 mV/decade subthreshold swing and considerably higher ON current compared to any state of the art FETs. Additionally, by the virtue of its ultra-thin body nature and electrostatic integrity, the 2D-EFET enjoys scaling beyond 10 nm technology node. The 2D-EFET works on the principle of voltage induced strain transduction. It uses an electrostrictive material as gate oxide which expands in response to an applied gate bias and thereby transduces an out-of-plane stress on the 2D channel material. This stress reduces the inter-layer distance between the consecutive layers of the semiconducting 2D material and dynamically reduces its bandgap to zero i.e. converts it into a semi-metal. Thus the device operates with a large bandgap in the OFF state and a small or zero bandgap in the ON state. As a consequence of this transduction mechanism, internal voltage amplification takes place which results in sub-60 mV/decade subthreshold swing (SS).

Proposal for an electrostrictive logic device with the epitaxial oxide heterostructure

“…This is referred to as an internal voltage amplification (i.e., ∂(� S +� E ) ∂qV GS > 1 ), arising from the interplay between the electrostatic and electrostrictive potentials. This leads to the sub-60 mV/decade subthreshold conduction as already simulated in the previous work, assuming the ideal interface between the piezoelectric oxide and channel layers 10 .…”

“…Electrostrictive FET works based on the principle of voltage-induced strain transduction by harnessing an electrostrictive (piezoelectric) material as a gate oxide layer that expands when exposed to an applied gate bias and consequently transduces an out-of-plane stress onto the adjacent channel material. Because this stress can change the electronic band structure of the semiconducting channel material (either bulk Si 5 or 2D material 10 ), the channel conductance could be modulated to provide the necessary ON/OFF switching for FET device operations. Owing to the internal feedback mechanism between electrostatic and electrostrictive potentials that gives rise to voltage amplification 10 , the sub-60 mV/decade subthreshold characteristic was predicted to appear in such an electrostrictive FET device structure.…”

“…By contrast, state-of-the-art "strain device" technology at that time, which was based on the use of materials with built-in stress or lattice mismatch, resulted in a constant strain; it was not possible to modulate strain with external means (e.g., the gate voltage bias in a FET structure). A more scalable approach was proposed in 2016 by using a modern FinFET structure adopting a semiconducting two-dimensional (2D) material as an electrostrictive FET channel 10 . In addition to its capability to achieve the SS of sub-60 mV/decade, the 2D material's ultra-thin body and electrostatic integrity 11 offered great promise for the technology nodes beyond 10 nm.…”

The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?

“…Conversely, the type of semiconductor in the body/channel strongly determines the performance of the -FET because of its electro-mechanical properties, which is not the case for the NC-FET. For example, a theoretical study in which transition metal dichalcogenides (TMDs) as a channel material in a -FET configuration was reported, referred to as the 2D-EFET [ 56 ], showing promising results.…”

Insights Into the Operation of Hyper-FET-Based Circuits

“…They can be stacked into the gate insulator of a MOSFET transistor to obtain a negative capacitance FET (NCFET) [5]- [8]. A two-dimensional electrostrictive field effect transistor (2D-EFET), which operation is also based on an internal voltage amplification enabled by using a electrostrictive material as gate oxide, has been also proposed [9]. Alternatively to the development of novel transistors, recently, Hybrid-phase-transition FETs (Hyper-FETs) have been proposed by connecting a phase transition material (PTM) to the source terminal of a FET.…”