Insights Into the Operation of Hyper-FET-Based Circuits

Abstract

Abstract-Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the I ON /I OFF ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called Hyper-FET to simulate different circuits, and to analyze the impact of the degraded DC output voltage levels of Hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements. We show that these estimations can reduce, cancel, or even lead to power penalties in low switching and/or low frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design.

Power and Speed Evaluation of Hyper-FET Circuits

“…This paper explores the first scenario. We combined a predictive 14nm High Performance (HP) FinFET transistor [21] (model available from [22]) with the PTM-Sim in [18], the characteristic parameters of which are shown in Table 1, as described in [19] and [20]. For the PTM-Sim, a Verilog-A model inspired by the macromodel proposed in [18] was derived.…”

“…During transitions, a single PTM switches to the metallic state, the p PTM for rising output transitions and the n PTM for falling output transitions. In the metallic state, the current through the Hyper-FET transistor is almost the same as the current through the transistor alone (see Fig 1c) and so no increase in delays is assumed [19], [20]. Once the output transition has taken place, the current decreases and the PTM which switched to the metallic state switches back to the insulating state.…”

“…Specifically, [19] showed that Hyper-FET logic gates exhibit degraded DC output voltages (different from V DD and zero). In [20], we analyzed the impact of these non-ideal voltage levels when interconnecting gates. Gates in a logic network were shown to deviate from their desired behavior, leading to smaller power savings than those predicted by gate level analysis or even to power penalties.…”

Hybrid-Phase-Transition FET Devices for Logic Computation

“…In [10] and [11], experiments were performed, which demonstrated the impact of these two factors. In this case, a HyperFET with an I OFF lower than that of its intrinsic Fin-FET and similar I ON (iso-I ON ) was evaluated.…”

“…They were also analyzed with an identical experimental setup. Because of the high impact of switching activity on power results reported in [10] and [11], the evaluations were done at the circuit level so that a realistic switching activity profile could be used.…”