Tutorial: Brain-inspired computing using phase-change memory devices

Abstract

There is a significant need to build efficient non-von Neumann computing systems for highly data-centric artificial intelligence related applications. Brain-inspired computing is one such approach that shows significant promise. Memory is expected to play a key role in this form of computing and, in particular, phase-change memory (PCM), arguably the most advanced emerging non-volatile memory technology. Given a lack of comprehensive understanding of the working principles of the brain, brain-inspired computing is likely to be realized in multiple levels of inspiration. In the first level of inspiration, the idea would be to build computing units where memory and processing co-exist in some form. Computational memory is an example where the physical attributes and the state dynamics of memory devices are exploited to perform certain computational tasks in the memory itself with very high areal and energy efficiency. In a second level of brain-inspired computing using PCM devices, one could design a co-processor comprising multiple cross-bar arrays of PCM devices to accelerate the training of deep neural networks. PCM technology could also play a key role in the space of specialized computing substrates for spiking neural networks, and this can be viewed as the third level of brain-inspired computing using these devices.

Comparing domain wall synapse with other non volatile memory devices for on-chip learning in analog hardware neural network

“…Scheme for conductance decrease-Conductance decrease is carried out by an abrupt RESET pulse that consumes 30pJ energy each [2], followed by a series of SET pulses (for conductance increase in small steps) much like RRAM synapse.…”

Lithium‐Battery Anode Gains Additional Functionality for Neuromorphic Computing through Metal–Insulator Phase Separation

“…In response to the growing prevalence of NN algorithms, there is increasing interest in developing “neuromorphic” hardware that mimics the brain and thus would naturally complement NN algorithms, enabling faster and more efficient execution. One promising approach is based on “memristors”, or circuit elements whose resistive state can be switched under high electric fields to store information, either by ionic migration or due to a phase‐change . For NN application, memristive devices must meet a number of requirements, admitting certain variability at the device level: µs‐ms switching timescales, relatively long state retention ≈10 5 s, and large number of addressable resistive states, which implies large resistance ratios ( R off / R on > 500).…”

On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network

“…However implementing NN on a traditional computer built on von Neumann architecture (memory and computing physically separated) involves continuous transfer of information between the memory and computing units. This von Neumann bottleneck leads to lower performance in terms of speed and energy consumption [2,3,4,5,6,7]. Hence researchers have come up with specialized hardware NN implementations to get rid of the von Neumann bottleneck [8,9,10,11].…”

“…Hence researchers have come up with specialized hardware NN implementations to get rid of the von Neumann bottleneck [8,9,10,11]. Among these implementations, analog hardware NN uses a crossbar array of synaptic devices to perform computing at the location of the data itself [5,6,12]. The fact that such crossbar array enables execution of Vector Matrix Multiplication (VMM), inherent in a FCNN algorithm, in a parallel fashion makes it suitable both for forward inference [5] or on-chip learning (training in hardware).…”

“…A synaptic device in a crossbar array based analog hardware NN must have several conductance states that can be controlled electrically to store and update the weight values of the NN. Several Non Volatile Memory (NVM) devices like floating gate transistors, chalcogenide based Phase Change Memory (PCM) devices, oxide based Resistive Random Access Memory (RRAM) devices and spintronic devices have been proposed and used as synaptic devices in previous implementations of analog hardware NN [5,6,7,13,14,15,16,17,18,19]. However, these NVM devices have several issues associated with them with respect to achieving on-chip learning in crossbar arrays made of them.…”