Resistive Random Access Memory (RRAM) and Phase Change Memory (PCM) devices have been popularly used as synapses in crossbar array based analog Neural Network (NN) circuit to achieve more energy and time efficient data classification compared to conventional computers. Here we demonstrate the advantages of recently proposed spin orbit torque driven Domain Wall (DW) device as synapse compared to the RRAM and PCM devices with respect to on-chip learning (training in hardware) in such NN. Synaptic characteristic of DW synapse, obtained by us from micromagnetic modeling, turns out to be much more linear and symmetric (between positive and negative update) than that of RRAM and PCM synapse. This makes design of peripheral analog circuits for on-chip learning much easier in DW synapse based NN compared to that for RRAM and PCM synapses. We next incorporate the DW synapse as a Verilog-A model in the crossbar array based NN circuit we design on SPICE circuit simulator. Successful on-chip learning is demonstrated through SPICE simulations on the popular Fisher's Iris dataset. Time and energy required for learning turn out to be orders of magnitude lower for DW synapse based NN circuit compared to that for RRAM and PCM synapse based NN circuits.

We have implemented a Spiking Neural Network (SNN) architecture using a combination of spin orbit torque driven domain wall devices and transistor based peripheral circuits as both synapses and neurons. Learning in the SNN hardware is achieved both under completely unsupervised mode and partially supervised mode through mechanisms, incorporated in our spintronic synapses and neurons, that have biological plausibility, e.g., Spike Time Dependent Plasticity (STDP) and homoeostasis. High classification accuracy is obtained on the popular Iris dataset for both modes of learning.

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We trained <b>Spiking neural network </b>(SNN) using <b>spike time dependent plasticity (STDP)</b>-enabled learning under two different learning schemes in <b>MNIST data set</b>(hand written digit recognition). We showed how the post-neurons need to be far more in number than the output classes for larger data sets in the case of SNN for reasonably high accuracy number. We have also reported the net energy consumed for learning in the spintronic devices and associated transistor-based circuits that enable synaptic functionality for this SNN.

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we have modeled domain-wall motion in ferrimagnetic and ferromagnetic devices through micro magnetics and shown that the domain-wall velocity can be 2–2.5X faster in the ferrimagnetic device compared to the ferromagnetic device. We also show that this velocity ratio is consistent with recent experimental findings Because of such a velocity ratio, when such devices are used as synapses in the crossbar-array-based fully connected network, our system-level simulation here shows that a ferrimagnet-synapse-based crossbar offers 4X faster (for the same energy efficiency) or 4X more energy-efficient (for the same speed) learning when compared to the ferromagnet-synapse-based crossbar.