Tunnel Magnetoresistance Effect

Jin, Ho; Miyazaki, T.

doi:10.1007/978-3-642-25583-0_12

Cited by 7 publications

(5 citation statements)

References 89 publications

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“…By contrast, the device's resistance is high in AP state. This phenomenon is well known as tunneling magneto-resistance effect [16,20], which is characterized by the TMR ratio. It is defined by: TMR = (R AP − R P )/R P , where R AP and R P are the resistances in AP and P states, respectively.…”

Section: Working Principlesmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This paper presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.

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Section: Working Principlesmentioning

confidence: 99%

Defect and Fault Modeling Framework for STT-MRAM Testing

Rao

Taouil

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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show abstract

“…This functionality means that the stored data in a memory cell can be read out and decoded into logic values in a certain form. For STT-MRAMs, this is realized by the Tunneling Magneto-Resistance (TMR) effect [75,88]. The TMR effect means that the resistance of MTJ depends on not only the TB thickness t TB , but also 3.1.…”

Section: Working Principlesmentioning

confidence: 99%

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Rao

Taouil

et al. 2021

2021 IEEE International Test Conference (ITC)

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“…These two binary magnetic states enable the MTJ device to store one-bit data. The resistance difference between the P and AP states is attributed to the tunneling magneto-resistance (TMR) effect [21][22][23]. The TMR effect can be simply interpreted by the band model [23] where the good band matching in the P state leads to large tunneling conductance (i.e., low resistance), while the poor band matching in the AP state results in less electrons tunneling through the barrier (i.e., high resistance).…”

Section: A Mtj Fundamentalsmentioning

confidence: 99%

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests

Wu,

Taouil,

Rao

et al. 2020

Preprint

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As one of the most promising emerging non-volatile memory (NVM) technologies, spin-transfer torque magnetic random access memory (STT-MRAM) has attracted significant research attention due to several features such as high density, zero standby leakage, and nearly unlimited endurance. However, a high-quality test solution is required prior to the commercialization of STT-MRAM. In this paper, we present all STT-MRAM failure mechanisms: manufacturing defects, extreme process variations, magnetic coupling, STT-switching stochasticity, and thermal fluctuation. The resultant fault models including permanent faults and transient faults are classified and discussed. Moreover, the limited test algorithms and design-for-testability (DfT) designs proposed in the literature are also covered. It is clear that test solutions for STT-MRAMs are far from well established yet, especially when considering a defective part per billion (DPPB) level requirement. We present the main challenges on the STT-MRAM testing topic at three levels: failure mechanisms, fault modeling, and test/DfT designs.

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Tunnel Magnetoresistance Effect

Cited by 7 publications

References 89 publications

Defect and Fault Modeling Framework for STT-MRAM Testing

Defect and Fault Modeling Framework for STT-MRAM Testing

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests

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