Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

Torralba, A.; Luján-Martínez, C.; Carvajal, R.G.; Galán, J.; Pennisi, Marzio; Ramírez-Angulo, J.; Lopez-Martin, A.J.

doi:10.1109/tcsii.2008.2010163

Cited by 34 publications

(14 citation statements)

References 13 publications

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“…Some recent works try to achieve G m -C filters comparable in terms of linearity to active-RC topologies, using passive resistors to perform the V-I conversion [6,7], mixed source degeneration structures formed by resistors and triode transistors [8,9], or cross-coupled MOS transistors [10]. Furthermore, techniques based on quasi-FGMOS (QFGMOS) transistors have been proposed for linearizing triode transistors in source degeneration structures [11].…”

Section: Design Techniques At Basic Cell Level (Transconductor)mentioning

confidence: 99%

“…The proposed method allows decreasing the number of active elements (transconductors) of the filter. Furthermore, techniques based on quasi-FGMOS (QFGMOS) transistors have been proposed for linearizing triode transistors in source degeneration structures [11].Concerning low-voltage low-power transconductor design, the use of the substrate as active terminal [12,13] or the use of FGMOS transistors for reducing the threshold voltage and compressing the signal swing to increase the operation range [14][15][16] are worth mentioning, to name a few techniques. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions.…”

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confidence: 99%

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Balanced G_m‐C filters with improved linearity and power efficiency

Algueta-Miguel

Blas

Lopez-Martin

2014

Circuit Theory & Apps

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A novel G m -C filter design technique is presented. It is based on floating-gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G m -C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all-pole G m -C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low-power second-order Butterworth G m -C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5-μm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. open-loop operation and the use of simpler topologies. However, these benefits come with the difficulty of achieving high linearity [4].Besides, the growing density of integration in CMOS technologies is reducing the thickness of the gate oxide of transistors, so supply voltages are also decreasing for reliability reasons: Voltages of 0.9 V are employed in modern technologies such as 90 nm and 65 nm, and the tendency is to keep decreasing. Furthermore, the growing proliferation of wireless and portable devices is leading to an intensive research on low-power integrated circuits for extending the lifetime of batteries.Thus, two challenging tasks are associated to G m -C filter design: linearity improvement to satisfy the modern communication standards and adaptation to the current low-voltage low-power requirements. Aimed to these goals, a novel G m -C filter design technique based on floating-gate MOS (FGMOS) transistors is proposed in this paper. It consists in a topological rearrangement of conventional filters without modifying the transconductor implementation and allows improving the filter linearity and relaxing the trade-off between the power consumption and the input range of the operational transconductance amplifier (OTA).The paper is organized as follows. In Section 2, an overview of several G m -C filter design methods available in the technical literature is presented. In Section 3, the fundamentals of the proposed FGMOS technique are explained, and considerations for applying it to G m -C filter design are discussed. The second-order effects of the presented method are studied in Section 4. In Section 5, a conventional second-order Butterworth G m -C filter is compared with its equivalent implementation obtained using the proposed design technique. Finally, conclusions are drawn in Section 6. All the proposed circuits have been fabrica...

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Section: Design Techniques At Basic Cell Level (Transconductor)mentioning

confidence: 99%

mentioning

confidence: 99%

Balanced G_m‐C filters with improved linearity and power efficiency

Algueta-Miguel

Blas

Lopez-Martin

2014

Circuit Theory & Apps

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“…Several FG based applications can be found out of which few are related to design of multiplier, transconductor, filter, I-V converter, CM with wide dynamic range and enhanced bandwidth and many other concerned to low voltage applications such as CM with enhanced bandwidth [7], CM with enhanced characteristics [8]. Taking advantage of capacitor divider property, some QFG based transistors were used for design of very linear programmable CMOS OTA [9] which further used to implement tunable MOS resistors [10] and also GM-C filter [11]. Other recent published articles are based on current conveyor [12], CM having low input compliance voltage [13].…”

Section: Gdmentioning

confidence: 99%

Low Power Circuit Design Techniques: A Survey

Raj¹,

Singh²,

Gupta³

2015

IJCTE

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Abstract-This paper presents a detail on various techniques to realize low voltage low power circuit. The techniques discussed are conventional gate-driven (GD), floating gate (FG), quasi-floating gate (QFG), bulk-driven (BD), and BD-QFG. The comparative analysis results in best performance achieved by BD-QFG approach. As BD circuits are well known approach for low power design, the combined effect QFG in bulk driven circuit results in enhanced performance. The complete analysis has been carried out in industry specific node UMC 0.18 micron technology with the help of HSpice simulator.

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“…The QFG principle is similar to the FG one with some variations; in case of FG the DC biasing point for the transistor is floating, whereas in QFG is not [27][28][29][30][31][32]. The no floating DC biasing point in case of QFG is achieved by connecting the gate of the transistor to a suitable bias voltage via a large-value resistor (R LARGE ), as illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

et al. 2017

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In this work, a new realization topology of the low-voltage ultra-low-power quadrature oscillator is presented. This quadrature oscillator utilizes only two active elements, namely differential voltage current conveyor (DVCC), and five passive ones, all of them are grounded, which is recommended for the integrated circuit implementation. The DVCC is based on quasi-floating-gate MOS transistor, which is a distinct technique from the conventional one, featuring with operation at low-voltage and ultra-low-power conditions; hence the proposed DVCC works with low supply voltage of ± 400 mV and consumes power of merely 6.6 µW. Thanks to these features the total power dissipation of the oscillator is only 0.28 mW. The simulation results using 0.18 µm TSMC CMOS technology are included in order to prove the design correctness.

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Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

Cited by 34 publications

References 13 publications

Balanced G_m‐C filters with improved linearity and power efficiency

Balanced G_m‐C filters with improved linearity and power efficiency

Low Power Circuit Design Techniques: A Survey

Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

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Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques

Cited by 34 publications

References 13 publications

Balanced Gm‐C filters with improved linearity and power efficiency

Balanced Gm‐C filters with improved linearity and power efficiency

Low Power Circuit Design Techniques: A Survey

Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

Contact Info

Product

Resources

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Balanced G_m‐C filters with improved linearity and power efficiency

Balanced G_m‐C filters with improved linearity and power efficiency