Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

Khateb, Fabian; Khatib, Nabhan; Koton, Jaroslav; Herencsár, Norbert

doi:10.24200/sci.2017.4377

Cited by 2 publications

(2 citation statements)

References 29 publications

(40 reference statements)

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“…Successive-approximation-register (SAR)-ADCs [4] have several circuitries like digital-to-analog circuits, control circuitries, and comparators. High resolution ADCs can be implemented with lesser complexity using sigma-delta (Σ∆) [5] counterparts but maintaining a good power efficiency is a challenging task [6]. Σ∆ ADCs produce an average output from a stream of bandlimited inputs.…”

Section: Introductionmentioning

confidence: 99%

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

2019

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The sampling rate plays a key role in wireless applications at very high-frequency range. Flash analog-to-digital converter (ADC) betters the slow converter counterparts in this regard but bulky at inevitable high resolutions. A state-of-the-art Divide and Collate (DnC) algorithm is proposed to design the flash ADC at subranging levels. The offset voltage is kept at a minimum through the comparators used for novel coarse and fine conversion separately. The kick-back noise is also reduced by using sample and hold switches at the input. The 10-bit ADC architecture is designed with 45-nm CMOS technology and analyzed in the SPECTRE environment. A trivial variation in the transconductance with temperature is observed and consequently the offset drift with temperature is found to be 0.015 mV/ • C. The design improves the INL by 0.42 LSB and DNL by 0.3 LSB. Signal-tonoise-and-distortion (SNDR) ratio and spurious-free-dynamic-range (SFDR) are 51.8 dB and 62 dB respectively at a frequency range near the Nyquist rate with a supply voltage of 1 V and input frequency of 500 MHz. Subranging scheme minimizes the comparator requirements which is reflected in the 44% reduction in the power dissipation.

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Section: Introductionmentioning

confidence: 99%

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

2019

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“…Using low-voltage small batteries with longer charge-discharge cycle is essential in todays portable equipements like cell phones, laptops, medical devices and etc [1][2][3][4][5]. Moreover, modern systems fabricated in deep sub-micron CMOS…”

Section: Introductionmentioning

confidence: 99%

0.3V Tunable OTA and Gm-C Filter in 0.13µm CMOS

Rezaei

2019

Scientia Iranica

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This paper presents an ultra-low-voltage operational transconductance amplifier (OTA) and Gm-C filter, both working with 0.3V single supply voltage. Using pseudo-differential structure, the common mode rejection is the main challenge in low voltage condition which is overcome by a new common mode feedback circuit. The OTA can be tuned through the gate terminal of body-driven PMOS input transistors. Post-layout simulation shows 23.4 dB differential gain and 47.4 dB CMRR at low frequencies. By changing the tune voltage from 50mV to 0V, the OTA's transconductance can be tuned from 7.9 to 17.4 µA/V . By applying input voltages up to 0.36 Vpp, the THD of output current remains less than -60 dB. The proposed OTA is employed to implement a tunable low-pass Gm-C filter. The cutoff frequency of Gm-C filter can be tuned from 1.13 to 1.9 MHz that makes it applicable in the multi-standard direct conversion receivers as channel selection filter. The power consumption of filter is 111.3 µW and its input referred voltage noise is 168.7 nV/ √ Hz, as results of post-layout simulations. The post-layout simulation shows the IIP3 of 8.5 dBm for the cutoff frequency of 1.9 MHz. Keywords Ultra-low-voltage design • Operational transconductance amplifier • Gm-C filter • layout • tunable IntroductionUsing low-voltage small batteries with longer charge-discharge cycle is essential in todays portable equipements like cell phones, laptops, medical devices and etc [1][2][3][4][5]. Moreover, modern systems fabricated in deep sub-micron CMOS

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Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

Cited by 2 publications

References 29 publications

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

0.3V Tunable OTA and Gm-C Filter in 0.13µm CMOS

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