TSV Transistor – vertical metal gate FET inside a Through Silicon VIA

Winkler, Felix; Killge, Sebastian; Fischer, D.; Richter, K.; Hiess, Andre; Bartha, Johann W.

doi:10.1109/led.2018.2864621

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…Next, a hole is etched with the assistance of a photoresist mask. An improved Bosch is employed for hole etching, followed by several steps to remove CF x polymers in the inside of the hole [27,28]. A SiO 2 layer is grown by thermal oxidation on the top of wafer, followed by a thermal atomic layer deposition (thALD) of Al 2 O 3 .…”

Section: Fabrication Processmentioning

confidence: 99%

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

et al. 2021

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In this paper, an innovative vertical MOSFET based on through-oxide via (TOV) technology is proposed for silicon-on-insulator (SOI)-based monolithic 3-D ICs. The proposed vertical MOSFET is investigated numerically. It was found that SOI can effectively reduce the parasitic capacitance, leakage current, power consumption, as well as suppress the pulse current interference of the substrate. The simulated results indicate that the proposed MOSFET possesses excellent characteristics in saturation current over 1500 μA, sub-threshold swing of 69 mV/dec, and on/off current ratio of 1.28 × 1011. Moreover, as temperature is a critical factor for the performance degradation of semiconductor devices, electrothermal simulations are conducted to predict the influence of the self-heating effect on device characteristics. The results show that device characteristics slightly deteriorate, but can still acceptable in their applications.

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Section: Fabrication Processmentioning

confidence: 99%

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

et al. 2021

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“…Based on TSV technology, miniaturized passive filters, couplers, power dividers and other functional components can be fabricated [1,2,3,4,5,6,7,8,9]. In order to meet the requirements of modern circuit system functions, the concept of TSV vertical switching has been proposed and simulated [10,11,12,13]. During the fabrication of the TSV, thermal stress is generated around the TSV after thermal annealing due to the different thermal expansion coefficients of various materials [14,15,16,17,18,19].…”

Section: Introductionmentioning

confidence: 99%

Effect of annealing residual stress on mobility of TSV vertical switch

Wang,

Ren,

Yin

et al. 2024

IEICE Electron. Express

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The effect of internal radial stress generated during the annealing process on the mobility of through-silicon via (TSV) vertical switch are analyzed in detail, by employing finite element software ANSYS and orthogonal experimental design method. The results show that, the TSV diameter has the largest effect on the mobility of the TSV vertical switch, while the equilateral triangle array produces the smallest effect of stress at the same distance.

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“…A possible application is the realization of a p‐through‐silicon via FET (TSVFET) with a hole diameter of several tens of micrometers that was only published as an n‐FET before. [ 14 ] Through silicon vias are often introduced in the presence of the metallization, [ 15 ] allowing only low thermal budgets for its fabrication. The moderate activation temperature of implanted gallium in silicon enables the fabrication of active device inside these holes.…”

Section: Introductionmentioning

confidence: 99%

The Doping of Si p‐Field‐Effect Transistor Devices by Gallium Focused Ion Beam Implantation Enabling Flexible Fabrication Routes at Moderate Temperatures

Winkler

Strobel

Wenzel

et al. 2020

Physica Status Solidi (a)

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A maskless approach of forming p-doped regions in Si wafers using the Ga source of a standard focused ion beam (FIB) system and the moderate activation temperatures of 400-700 C is demonstrated in this work. This simple and flexible route is accessible to many research labs and is successfully used to fabricate Si-based diodes and field-effect transistors (FETs). For the diodes, tunneling is found to be the forward current transport mechanism. The fabricated p-FET structures show excellent switching behavior with a high I D,ON /I D,OFF current ratio of 5 Â 10 6 .

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TSV Transistor – vertical metal gate FET inside a Through Silicon VIA

Cited by 6 publications

References 11 publications

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

Effect of annealing residual stress on mobility of TSV vertical switch

The Doping of Si p‐Field‐Effect Transistor Devices by Gallium Focused Ion Beam Implantation Enabling Flexible Fabrication Routes at Moderate Temperatures

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