Trends in megabit DRAM circuit design

Sixteen-megabit dynamic random access memory trench depth characterization using two-dimensional diffraction analysis

“…1 Figure 2 illustrates the increase in approximate DRAM chip size as a result of the increase in the number of trenches. 3 Alternative new methods for increasing cell charge capacity without increasing cell depth include reducing the dielectric thickness or increasing the dielectric constant. 4 However, reducing the nitride thickness below 6 nm causes sudden drops in capacitance, 5,6 while adopting materials with higher dielectric constants, e. g., tantalum pentoxide ͑Ta 2 O 5 ͒, results in higher leakage current levels.…”

High resolution optical lithography or high throughput electron beam lithography: The technical struggle from the micro to the nano-fabrication evolution

“…55 Not only the integration level of ULSI devices, but also the perfor- 56 mance of devices has improved drastically [5]. 57 In the first 30 years, the miniaturization of ULSI was led by the 58 development of DRAM devices [6]. This paper discusses the devel- 59 opment of lithographic technology mainly through the perspective 60 of the miniaturization of DRAM devices.…”

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories

“…Significant amount of work has been done in the recent years to obtain fast and very large memory systems. As a result, the density of semiconductor memory chips has increased dramatically [1]. With the increasing complexity, it has been recognized that the efficient testing of such memories is a difficult problem.…”

“…Because the complexity of memories is quadrupling in every 2-3 years, even a linear increase in test time becomes undesirable for large memories [1].…”