We present a design method (called STD architecture) to design large memories so that the test time does not increase with the increasing size of memory. Large memories can be constructed by using several small blocks of memory. The memory address decoder is divided into two or more levels and designed such that during the test mode all small memory blocks are accessed together. With
Since the first flash memory patent issued on October 6, 1987, flash memory's multiple usehl characteristics, including nonvolatility, in-circuit reprogrammability, low power consumption, and high density,
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