Trends in low power digital system-on-chip designs

Saleh, R.; Lim, Gwon; Kadowaki, T.; Uchiyama, Kunio

doi:10.1109/isqed.2002.996775

Cited by 14 publications

(12 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The generic gate delay, τ delay , (using logical effort [7]) is calculated with equation (1). (1) In the clocked delay PLA's critical path we have a chain of gates whose total delay is given in equation (2).…”

Section: A Pla Critical Path Calculationsmentioning

confidence: 99%

See 1 more Smart Citation

Structured Logic Arrays for Future CMOS Technologies

Mehrabadi

Yuan

Saleh

2007

2007 Canadian Conference on Electrical and Computer Engineering

View full text Add to dashboard Cite

As we continue to scale the dimensions of transistors and wires in the deep submicron (DSM) era, the resolution of photolithographic processes is quickly reaching its limits and causing problems in the reliable manufacture of integrated circuits. The design methods using standard cell ASICs (SC-ASIC) produce randomly placed gates and interconnects which are difficult to fabricate at fine geometries, such as 65nm and below. Besides reduced yield, they also suffer from high testing cost, even with the most advanced built-in self-test methods. These shortfalls motivated us to search for more structured logic architectures for future technologies that can be fabricated more easily and are better suited to self-test, and eventually self-repair. In this paper, we focus on programmable logic arrays to explore their potential when competing for speed, area and power with SC-ASIC. We will investigate the critical path delay for clockdelayed PLAs and provide equations for quick estimation of capacitive loads, delays and areas using technology-independent parameters. These equations can be used in front-end CAD tools for partitioning and architecture decision-making before the logic is implemented in a specific technology. We analyse the PLA to determine optimal sizes for logic implementation. We find that circuits with higher than 200 product terms have slower PLA implementations than SC-ASIC. They often take more than 10 times the area of SC-ASIC designs. To overcome these problems, we introduce methods to subdivide the slower PLAs in order to improve the overall circuit timing and area. For example, by dividing a circuit into two PLAs, we can cut its delay by half and keep the increase in area minimal.

show abstract

Section: A Pla Critical Path Calculationsmentioning

confidence: 99%

“…To take advantage of the unused silicon area that the deepsubmicron technologies make available, very often extra memory blocks are integrated into the chips [1]. Memories are structured arrays, which can easily be produced using CAD tools known as memory compilers [2].…”

Section: Introductionmentioning

confidence: 99%

Structured Logic Arrays for Future CMOS Technologies

Mehrabadi

Yuan

Saleh

2007

2007 Canadian Conference on Electrical and Computer Engineering

View full text Add to dashboard Cite

show abstract

“…Indeed, the transistor miniaturization dramatically increases the power consumed by a whole chip [5]. The main consequences of this trend are the addition of cooling circuits and the battery lifetime reduction for embedded systems.…”

Section: Introductionmentioning

confidence: 99%

A high level SoC power estimation based on IP modeling

Elleouet

Julien

Houzet

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

View full text Add to dashboard Cite

Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is estimated after RTL synthesis. We propose in this article a methodology based on measurements which allows to model the application power consumption with architectural and algorithmic parameters. So, the modeled applications can be added in a library in order to help the system designer to determine early in the design flow the best adequacy between high performances and low power consumption.

show abstract

“…In 2001, memories in SoCs have already accounted for over 60% of the silicon area [1]. The percentage is fast growing and is expected to rise to 94% by 2016 [9,11]. Memory test in such an environment faces many challenges.…”

Section: Introductionmentioning

confidence: 99%

“…These proposals all use a gray code address generator instead of binary code in order to minimize signal activities in memory address decoders. Except for very small memories, however, power dissipation in decoders is often a negligibly small portion of total memory power [7][8][9]. In comparison, power dissipation on the memory data path constitutes significant percentage of total memory power [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Low Power SoC Memory BIST

Ivanov

2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

View full text Add to dashboard Cite

With the ever increasing number of memories embedded in a System-on-Chip (SoC), power dissipation due to test has become a serious concern. This paper studies power dissipation in SRAMs and proposes a novel low power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies. As demonstrated, up to 30% power reduction can be achieved with virtually zero hardware overhead.

show abstract

Trends in low power digital system-on-chip designs

Cited by 14 publications

References 2 publications

Structured Logic Arrays for Future CMOS Technologies

Structured Logic Arrays for Future CMOS Technologies

A high level SoC power estimation based on IP modeling

Low Power SoC Memory BIST

Contact Info

Product

Resources

About