Low Power SoC Memory BIST

Wu, Yuejian; Ivanov, A.

doi:10.1109/dft.2006.39

Cited by 7 publications

(1 citation statement)

References 16 publications

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“…With the ever-increasing number of memories embedded in a system on chip (SoC), power dissipation due to memory test has become a serious concern. In [42], the authors proposed a novel low-power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies.…”

Section: By Separate Testing Strategy For Memorymentioning

confidence: 99%

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

2011

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Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.

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Section: By Separate Testing Strategy For Memorymentioning

confidence: 99%