Trap and self-heating effect based reliability analysis to reveal early aging effect in nanosheet FET

Rathore, Sunil; Jaisawal, Rajeewa Kumar; Kondekar, P. N.; Bagga, Navjeet

doi:10.1016/j.sse.2022.108546

Cited by 20 publications

(7 citation statements)

References 18 publications

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“…The baseline FDSOI device, as shown in figure 1, is simulated using the Sentaurus TCAD tool [44]. A drift-diffusion model is considered for carrier transport, consistent with the existing literature, including for devices of smaller channel lengths [46][47][48][49][50][51]. Due to having variation in between source/drain channel doping in the lateral direction, which impacts the bandgap at the junctions, a bandgap narrowing effect is included in the simulations.…”

Section: Simulations and Benchmarking Of Baseline Fdsoi Devicementioning

confidence: 99%

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Kansal,

Medury

2024

Semicond. Sci. Technol.

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Dielectrically modulated (DM) Negative Capacitance Field Effect Transistor (NCFET) based label-free Biosensors have emerged as promising devices for accurate detection of various biomolecules, where the sensitivity of DM architectures strongly depends on the sensing mechanism as well as on the size of the nano-cavity. Therefore, to achieve higher sensitivity along with reduced fabrication complexity, we propose to utilize a pre-existing drain-sided spacer region as a nano-cavity, in a Fully Depleted Silicon-on-insulator (FDSOI) based NCFET architecture. The Ferroelectric (FE) layer in the Metal-Ferroelectric-Insulator-Semiconductor (MFIS) configuration meaningfully alters the impact of drain's electric field on the source-sided electrostatics, which results in higher sensitivity. Having quantified the sensitivity for an FE-DE gate stack based NCFET Biosensor, we now propose to include a Paraelectric (PE) layer between Ferroelectric (FE) and Dielectric (DE) materials, thus modifying the gate stack from FE-DE to FE-PE-DE with an equivalent negative capacitance seen from both the stacks, where a remarkable improvement is seen in the FE-PE-DE gate stack based NCFET with nearly identical linearity performance as seen from the high value of Pearson's coefficient (r2 ≥ 0.9). Therefore, in order to illustrate the efficacy of the proposed sensing mechanism and the modified gate stack (FE-PE-DE), dielectric constant (kBio) values in the range of kBio = 4.5 to kBio = 75.99 are considered. Finally, the effect of scaling the channel length (Lg) on the sensitivity of the FE-PE-DE NCFET device is shown and a high value, particularly at lower permittivity, demonstrates the versatility and wide applicability of the proposed NCFET Biosensor.

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Section: Simulations and Benchmarking Of Baseline Fdsoi Devicementioning

confidence: 99%

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

Kansal,

Medury

2024

Semicond. Sci. Technol.

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“…Moreover, the QGFETs suffer from corner effects. Owing to the challenges presented in above devices, the GAA structures has gained traction due to their ability to provide excellent electrostatic control, mitigating issues associated with SCEs, and improving the transistor's overall performance [15,16]. The Cylindrical GAA FET is characterized by its unique architecture, in which the gate electrode fully surrounds the channel region of the transistor.…”

Section: Introductionmentioning

confidence: 99%

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Mudidhe,

Nistala

2023

Phys. Scr.

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The GAA FET has emerged as a promising device due to its excellent control over short-channel effects and improved electrostatic control. This manuscript presents the analytical modelling for the Dual Material Graded Channel (DMGC) Cylindrical GAA FET to characterize the drain current in linear, saturation, as well as subthreshold regions. The model incorporates the effect of supply voltage, radius, and thickness of oxide layer on the device enabling a comprehensive analysis of the device behaviour. The influence of subthreshold swing is also presented. Next, the analysis is extended to investigate the important analog performance parameters that includes transconductance and output conductance. The validation of the analytical model across a wide range of operating conditions with the simulated data is performed and observed to be a close match. Building upon the insights gained from the analytical modelling, a common source amplifier based on the DMGC CGAA FET is designed. The amplifier's performance has been optimized by carefully selecting the biasing conditions and a maximum gain value of 7.745 is achieved. Further, an improvement of 42.28% in output voltage is observed for DMGC in comparison with SMGC making it a promising device for high-performance integrated circuit design.

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“…Recently, researchers have investigated the interface traps including self-heating effects on devices like MOSFET [17], FinFET [18], Nanosheet FET [19], TFET [20] revealing further deterioration in devices performance in presence of SHE. Hsieh et al [21] experimental findings suggested a novel Random telegraph noise (RTN) method to measure SHE induced channel temperature of the device.…”

Section: Introductionmentioning

confidence: 99%

Physical insights of interface traps and self-heating effect on electrical response of DMG FinFETs in overlap and underlap configurations: analog/RF perspective

Chaudhary,

Saha

2023

Phys. Scr.

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This paper presents a thorough analysis on analog/RF parameters including interface trap charges (ITCs) of two different densities of states (DOS) along with self-heating on the performance of DMG FinFETs in Overlap and Underlap configurations. Initially, the independent simulations for acceptor ITCs and Self-heating in conventional device reveals that performance degradation caused by Self-heating is more prominent (25.03%) than uniform acceptor ITCs (9.46%). In consecutive step, the cumulative impact of both acceptor ITCs and Self-heating on DC and RF/analog parameters are carried out. Investigation reveals that as the impact of self-heating is larger in overlap configuration, the degradation in drain current is higher in overlap configuration (45.2%, 54.5%) as compared to conventional (30.4%, 40.96%) and underlap (37.2%, 52.8%) configurations for both Uniform and Gaussian trap distributions, respectively.

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Trap and self-heating effect based reliability analysis to reveal early aging effect in nanosheet FET

Cited by 20 publications

References 18 publications

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

A negative capacitance field effect transistor with a modified gate stack and drain-side cavity for label-free biosensing

An analytical drain current modelling of DMGC CGAA FET: A circuit level implementation

Physical insights of interface traps and self-heating effect on electrical response of DMG FinFETs in overlap and underlap configurations: analog/RF perspective

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