Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS

Hernandez, Raul Acosta; Strum, Marius; Chau, Wang Jiang

doi:10.1109/latw.2015.7102518

Cited by 5 publications

(1 citation statement)

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“…A method based on a formal attribute grammar, used to translate human language into correct Computation Tree Logic from specific comments in the HDL code, is described in [18]. Transformations of the behavioral RTL FSMD model are proposed in [19] in order to deal with false negative results of the equivalence checking of state sequences from conditional paths in equivalent checking. Static and dynamic analysis of the RTL source code is exercised in [20] to define and compute code coverage of assertions in the RTL code.…”

Section: Wwwetasrcom Dossis: High-level Synthesis Integrated Verifica...mentioning

confidence: 99%

High-level Synthesis Integrated Verification

Dossis¹

2015

Eng. Technol. Appl. Sci. Res.

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It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.

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Section: Wwwetasrcom Dossis: High-level Synthesis Integrated Verifica...mentioning

confidence: 99%