High-level Synthesis Integrated Verification

Dossis, Michael

doi:10.48084/etasr.596

Cited by 3 publications

(3 citation statements)

References 18 publications

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“…The research endeavor was inaugurated with the conceptualization and realization of the 32bit ALU, tailored for integration within a processor architecture, as illustrated in Figs. 1 and 2 (Alshortan et al, 2021;Alrashdi and Khan, 2022;Durrani et al, 2016;Dossis, 2015).…”

Section: Introductionmentioning

confidence: 99%

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

Alshortan,

Almalaq,

Khan

2023

Int. j. adv. appl. sci.

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This research paper investigates the influence of different initial design techniques on the area, timing, and power aspects of technology-mapped designs. As a practical case study, we undertake the design and analysis of a 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, a fundamental component of all processors, comprises three major units: the Adder responsible for signed and unsigned number addition and subtraction, the Logic unit which handles bitwise logical operations, and the Shifter unit facilitates arithmetic and logical shift operations. The two adder designs are based on the ripple carry method (ALU_RCA) and the Sklansky method (ALU_SKL), respectively. The design and analysis process involved utilizing established toolsets from Cadence, including NCSIM for simulation and verification, RTL Compiler for logic synthesis, static timing analysis and power estimation, and SOC encounter tool for floorplanning and layout. Through this investigation, we aim to shed light on the varying performance implications of different initial design approaches in technology-mapped designs.

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Section: Introductionmentioning

confidence: 99%

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

Alshortan,

Almalaq,

Khan

2023

Int. j. adv. appl. sci.

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“…But then, the first design approach was chosen as including six 32-bit muxes would take up too much area and would probably kill the basic idea of saving power consumption. [25][26][27][28][29][30]. Block diagram of a 32-bit ALU II.…”

Section: Introductionmentioning

confidence: 99%

“…A simulation was then run on a test vector set and signal switching activity was written into a VCD file. This file was compiled by an RTL compiler to obtain "real" switching information in the power analysis [28][29][30].…”

Section: Introductionmentioning

confidence: 99%

Design and Comparative Analysis of High Speed and Low Power ALU Using RCA and Sklansky Adders for High-Performance Systems

Alrashdi

Khan

2022

Eng. Technol. Appl. Sci. Res.

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This study examines how different initial design decisions affect the area, timing, and power of technology-mapped designs. ASIC design flow, tools used during the flow, and the factors to consider to maximize the performance and power ratio are discussed. The ALU (Arithmetic Logic Unit) is a fundamental part of all processors. In this study, two ALUs were implemented using two different types of adder circuits: a Ripple Carry Adder (RCA) and a Sklansky adder. The Cadence EDA tools were used for the implementation. A comparative analysis was conducted for the two designed ALUs in terms of area, power, and timing analysis. The ALU design was also used as an example to examine the whole workflow front-end wise by constructing a block schematic and back-end wise by floorplanning, placing, and routing the physical design.

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Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits

K.P

et al. 2023

ITM Web Conf.

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High-level synthesis (HLS) is utilized for high-performance and energy-efficient heterogeneous systems designing. HLS is assist in field-programmable gate array circuits designing where hardware implementations are refined and replaced in target device. However, the power-process-voltage-temperature-delay (PPVTD) variation in VLSI circuits undergoes many problems and reduced the performance. In order to address these problems, C4.5 with eXtreme Gradient Boosting Classification based High Level Synthesis (C4.5-XGBCHLS) Method is designed for afford better runtime adaptability (RA) with minimal error rate. VLSI circuits are designed using the behavioral input and results are measured at running condition. When VLSI circuit’s results get reduced, the language description of the circuit is considered as an input. Then, compilation process convert high level specification into Intermediate Representation (IR) in control/data flow graph (CDFG). CDFG computes data and control dependencies among operations. eXtreme Gradient Boosting (XGBoost) Classifier is exploited in C4.5-XGBCHLS method to classify the error causing functional unit (FU) with minimal error rate. XGBoost Classifier exploited C4.5 decision tree as base classifier to enhance classification of error causing FU in VLSI circuits. After that, FU gets allocated in place of error causing FU from functional library based on the design objectives and PPVTD variations. Finally, operation scheduling and binding process is executed for register transfer level (RTL) generation to form VLSI circuits with improved RA. The simulation results shows that the C4.5-XGBCHLS method enhances the performance of functional unit selection accuracy (FUSA) with minimal error rate (ER) and circuit adaptability time (CAT).

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High-level Synthesis Integrated Verification

Cited by 3 publications

References 18 publications

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

Design and Comparative Analysis of High Speed and Low Power ALU Using RCA and Sklansky Adders for High-Performance Systems

Integrated extreme gradient boost with c4.5 classifier for high level synthesis in very large scale integration circuits

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