Transaction-level models for AMBA bus architecture using SystemC 2.0

Caldari, M.; Conti, Massimo; Coppola, Marcello; Curaba, Stephane; Pieralisi, Lorenzo; Turchetti, Claudio

doi:10.1109/date.2003.1253800

Cited by 62 publications

(38 citation statements)

References 4 publications

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“…For delay computations, we use our gate delay model [17] described in Section III-A below. Current literature on bus modeling such as [25], [24], [23] are focused at RTL or higher level (i.e., transaction level) whereas we propose physicallevel models to estimate delay, power, and area. Our models can be plugged into any high-level synthesis tool or network simulator to aid in estimation of metrics.…”

Section: Logic Modelingmentioning

confidence: 99%

On modeling and sensitivity of via count in SOC physical implementation

Jeong

Kahng

Yao

2008

2008 International SoC Design Conference

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Abstract-Multiprocessor systems-on-chip (MPSoCs) are emerging as a popular SoC design platform. However, major challenges arise from nonscaling global wire delay and from the reuse of intellectual properties (IPs) from different vendors to meet tight time-to-market constraints. Designing the appropriate communication fabrics for such heterogeneous systems becomes a challenging task. In this paper, we present accurate delay, power, and area models for bus-based and packetswitched communication architectures. We also integrate our models into the COSI-OCC [30] predicts that future generations of high-end IC designs will operate in the 10-20 GHz range, with multi-Gbit/s communication between cores. A major challenge designers face is to provide a reliable and functional interconnection between the components of the design [1].As device sizes shrink to keep up with Moore's Law, major challenges arise from non-scalable global wire delays. Recently, designers have moved from a computation-centric view of chip design to a communication-centric view, largely due to the increasing significance of interconnect delay versus gate delay in current and future technologies. Based on the premise that interconnection technology will be a limiting factor for achieving SoC operational goals, we propose a characterization framework for the two most dominant interconnection architectures in today's designs: (1) busbased architecture (i.e., shared medium) and (2) packet-switched architecture (i.e., as employed in current NoC designs). We review each of these architectures and then propose accurate and fast systemlevel models for performance, power, and area to aid fast and efficient design space exploration. For bus-based designs, we develop models for AMBA (Advanced Microcontroller Bus Architecture) [29], a popular on-chip bus for ARM processors. For NoC-based designs, we integrate our proposed models into the COSI-OCC communication synthesis tool [19] and show they substantially change the NoC outcome of system-level design exploration. Because state-of-the-art communication architectures are quite complex, with multiple components, there has been little research on modeling and early-designstage prediction. In this context, we have developed an integrated communication modeling library that:• models popular low-and high-level communication structures, • predicts delay, power, and area at early design stage with as much accuracy as feasible, • is usable by system-level designer, and • allows technology extrapolation. In this invited paper, we have integrated content from our previous works [16], [17], [18]. Section II describes the current state-of-theart bus-based communication architectures and proposes accurate delay, power, and area models for such architectures. Section III describes network-on-chip communication architectures and presents our modeling approach through two examples of physical link and router power modeling. Section IV shows the impact of increased accuracy of our models on system-level design choices and...

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Section: Logic Modelingmentioning

confidence: 99%

On modeling and sensitivity of via count in SOC physical implementation

Jeong

Kahng

Yao

2008

2008 International SoC Design Conference

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“…The AMBA AHB bus can be decomposed in the following main blocks: one arbiter, a decoder and some multiplexing logic for read and write operations. The AMBA AHB bus has been described in SystemC 2.0 and in VHDL in a clock accurate description [10][11]. The number of bits of ADDR and DATA lines, and the number of masters and slaves connected to the bus are parameters that can be easily changed in the SystemC code.…”

Section: Amba Bus Vhdl and Systemc Modelsmentioning

confidence: 99%

Performance analysis of different arbitration algorithms of the AMBA AHB bus

Conti

Caldari

Vece

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

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Bus performances are extremely important in a platform-based design. System Level analysis of bus performances gives important information for the analysis and choice between different architectures driven by functional, timing and power constraints of the System-on-Chip. This paper presents the effect of different arbitration algorithms and bus usage methodologies on the bus AMBA AHB performances in terms of effective throughput and power dissipation. SystemC and VHDL models have been developed and simulations have been performed.

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“…In particular, the advanced microcontroller bus architecture (AMBA) of ARM is conventionally used in a number of systems since it is a good architecture for applying embedded systems with low power [3]. Also, many researches related with the AMBA bus have been proposed, such as multiclock operations [4], a wrapper design [5], multi-processor design [6], and system level modeling [7]. Moreover, the ML-AHB BusMatrix allows a number of masters to communicate with a number of slaves in a system.…”

Section: Introductionmentioning

confidence: 99%