TRAM: A tool for Temperature and Reliability Aware Memory Design

Khajeh,; Gupta, Rajiv; Dutt, Nikil; Kurdahi, Fadi; Eltawil, Ahmed M.; Khouri,; Abadir,

doi:10.1109/date.2009.5090685

Cited by 2 publications

(1 citation statement)

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“…They result in a temperature reduction of up to 13 o C for some benchmarks in L1 Data cache and up to 10 o C in the shared L2. 10 o C temperature reduction in large caches translates to additional 7% leakage reduction and 5-10x reduction in probability of failure [18]. Applying the two techniques also results in a large reduction in maximum temperature difference in L1 and L2 caches.…”

Section: Discussionmentioning

confidence: 99%

Hot peripheral thermal management to mitigate cache temperature variation

Homayoun

Rahmatian

Kontorinis

et al. 2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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Abstract-Modern microprocessor caches are often regarded as cool chip components that dissipate power uniformly. This research demonstrates that this uniformity is a misconception. Memory cell peripherals dissipates considerably higher power than the actual memory cell and this can result in up to 30 o C of temperature difference between the warmest and the coolest cache part. To be effective and accurate, cache temperature and power modeling and management must take this effect into account. We focus on the surrounding logic of the memory cell and apply two novel techniques, peripheral bit swapping (PBS) and peripheral monitor and shutdown (PMSD), to reduce the thermal variation and reduce the corresponding steady-state temperature and leakage power of the cache. Overall, our techniques, on average, decrease temperature by 8 o C for the L1 Data Cache and 5 o C for the shared L2 cache and reduce their thermal gradient by more than 75%, on average, and across SPEC2K benchmarks.I.

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Section: Discussionmentioning

confidence: 99%