Trace processors

Rotenberg, Eric; Jacobson, Quinn; Sazeides, Yiannakis; Smith, James E.

doi:10.1109/micro.1997.645805

Cited by 192 publications

(143 citation statements)

References 16 publications

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“…In order to avoid storing every block in full, the HBA core uses an instruction cache (as in the baseline), and stores only block metadata in a block info cache. This cache is indexed with the start PC of a block and its branch path, just as in a conventional trace cache [47,42]. The block info cache stores information that the core has discovered about the block.…”

Section: Atomicitymentioning

confidence: 99%

“…The use of a block info cache in parallel with a conventional instruction cache, rather than a full trace cache [47,42], allows the HBA core to achieve the best of both worlds: it achieves the space efficiency of the instruction cache while retaining the learned information about code blocks (enabling the core to leverage fine-grained heterogeneity between blocks).…”

Section: Block Core Designmentioning

confidence: 99%

“…Full Block Cache Recall that HBA uses a block info cache that stores only metadata for each code block, without storing the block's instructions. This design saves space (a cache of 1024 blocks requires 256 KB of storage), but cannot achieve the higher fetch rates that are possible if pre-formed blocks are fetched [24,47].…”

Section: Block Info Cachementioning

confidence: 99%

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The heterogeneous block architecture

Fallin¹,

Wilkerson

Mutlu³

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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This paper makes two new observations that lead to a new heterogeneous core design. First, we observe that most serial code exhibits fine-grained heterogeneity: at the scale of tens or hundreds of instructions, regions of code fit different microarchitectures better (at the same point or at different points in time). Second, we observe that by grouping contiguous regions of instructions into blocks that are executed atomically, a core can exploit this heterogeneity: atomicity allows each block to be executed independently on its own execution backend that fits its characteristics best.Based on these observations, we propose a fine-grained heterogeneous design that combines heterogeneous execution backends into one core. Our core design, the heterogeneous block architecture (HBA), breaks the program into blocks of code, determines the best backend for each block, and specializes the block for that backend. As an initial, concrete design, we combine out-of-order, VLIW, and in-order backends, using simple heuristics to choose backends. We compare HBA to multiple baseline core designs (including monolithic out-of-order, clustered out-of-order, in-order and a state-of-the-art heterogeneous core design) and show that HBA can provide significantly better energy efficiency than all designs at similar performance. Averaged across 184 traces from a wide variety of workloads, HBA reduces core power by 36.4% and energy per instruction by 31.9% compared to a 4-wide out-of-order core. We conclude that HBA provides a flexible substrate for exploiting fine-grained heterogeneity, enabling new energy-performance tradeoff points in core design.

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Section: Atomicitymentioning

confidence: 99%

Section: Block Core Designmentioning

confidence: 99%

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The heterogeneous block architecture

Fallin¹,

Wilkerson

Mutlu³

2014

2014 IEEE 32nd International Conference on Computer Design (ICCD)

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“…A machine that follows the trace cache architecture [30] fetches instructions from the instruction cache and attempts to schedule and execute them across multiple functional units using, for example, Tomasulo's algorithm [36]. During this process, the instructions are saved into the trace cache, which stores them in execution order, as opposed to the static order determined by the compiler.…”

Section: Other Approaches For Exploiting Ilpmentioning

confidence: 99%

Dynamically Scheduling VLIW Instructions

Souza

Rounce

2000

Journal of Parallel and Distributed Computing

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Very long instruction word (VLIW) machines potentially provide the most direct way to exploit instruction-level parallelism; however, they cannot be used to emulate current general-purpose instruction set architectures. In addition, programs scheduled for a particular implementation of a VLIW model cannot be guaranteed to be binary compatible with other implementations of the same machine model with a different number of functional units or functional units with different latencies. This paper describes an architecture, named dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility. Preliminary measurements of the DTSVLIW performance, obtained with an execution-driven simulator running the SPECint95 benchmark suite, are also presented. Academic Press

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“…Many techniques have been proposed to create large ROB and instruction queues, such as the multiscalar processor [31], the trace processor [27], and the DMT architecture [2]. These architectures allow speculative execution of a large number of instructions.…”

Section: Related Workmentioning

confidence: 99%