Out-of-Order Commit Processors

Cristal, Adrián; Ortega, Daniel; Llosa, Josep; Valero, Mateo

doi:10.1109/hpca.2004.10008

Cited by 106 publications

(77 citation statements)

References 23 publications

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“…Other out-of-order retirement uniprocessor architectures have been devised, including work by Cristal et al [3], Akkary et al [1], and Bell et al [2]. However, to the best of our knowledge, no checkpoint-free out-of-order retirement architecture has been adapted and evaluated in a multiprocessor environment, especially when memory consistency is also considered.…”

Section: Related Workmentioning

confidence: 99%

“…To support this ability, any instruction renaming (i.e., writing to) a given logical register holds in its HB entry two values. The first entry is the identifier l of its destination logical register; the second is the value of l before it was rewritten, that is, the contents of physical register p (i.e., RF [p ]) that were produced by the nearest previous (in program order) instruction renaming l, being p the previous mapping of l 3 . Following this implementation, whenever a cache block accessed by a non-globally performed memory instruction is being remotely accessed or evicted, execution is recovered by squashing the contents of the ROB and undoing the changes logged in the HB.…”

Section: Dealing With Sequential Consistencymentioning

confidence: 99%

“…This class of processors were originally proposed [1][2] [3] as an effective solution to increase the instruction window size by relaxing the conditions under which instructions are retired from the pipeline. In this context, the Validation Buffer (VB) architecture has been proposed and evaluated for superscalar microarchitectures [4].…”

Section: Introductionmentioning

confidence: 99%

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A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

Ubal

Sahuquillo

Petit

et al. 2012

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Out-of-order retirement of instructions has been shown to be an effective technique to increase the number of in-flight instructions. This form of runtime scheduling can reduce pipeline stalls caused by head-of-line blocking effects in the reorder buffer (ROB). Expanding the width of the instruction window can be highly beneficial to multiprocessors that implement a strict memory model, especially when both loads and stores encounter long latencies due to cache misses, and whose stalls must be overlapped with instruction execution to overcome the memory latencies.Based on the Validation Buffer (VB) architecture (a previously proposed out-of-order retirement, checkpoint-free architecture for single processors), this paper proposes a cost-effective, scalable, out-of-order retirement multiprocessor, capable of enforcing sequential consistency without impacting the design of the memory hierarchy or interconnect. Our simulation results indicate that utilizing a VB can speed up both relaxed and sequentially consistent in-order retirement in future multiprocessor systems by between 3% and 20%, depending on the ROB size.

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Section: Related Workmentioning

confidence: 99%

Section: Dealing With Sequential Consistencymentioning

confidence: 99%

See 1 more Smart Citation

A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

Ubal

Sahuquillo

Petit

et al. 2012

IEEE Trans. Parallel Distrib. Syst.

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“…Otherwise they have low execution locality. This observation enables the construction of large-window processors requiring only moderately-sized structures by focusing only on the execution of high locality code [7,16,30,23].…”

Section: Recent Trends In Ilp Processorsmentioning

confidence: 99%

“…Work in this field has concentrated on the reorder buffer [7,1], the instruction queues [7,16,30], on handling registers [19,6] and on the load/store queue. Load queue resource requirements can be greatly reduced by using techniques for early release of load instructions [8,18].…”

Section: Related Workmentioning

confidence: 99%

A Flexible Heterogeneous Multi-Core Architecture

Pericas¹,

Cristal²,

Cazorla³

et al. 2007

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

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Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization

Sharkey

Ponomarev

Ghose

et al. 2005

Power-Aware Computer Systems

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Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay and energy requirement of driving the result tags across the associatively-addressed issue queue accounts for a significant percentage of the scheduler's overhead and also limits the design scalability. We propose two schemes to reduce the power consumption and the delays of the wakeup logic. Our first scheme-instruction packing-shares the associative part of an issue queue entry between two instructions, each with at most one non-ready source. As a result, the number of entries in the issue queue (and, hence, the length of the tag buses) can be reduced by a factor of two with almost no impact on the IPCs, because most instructions either enter the pipeline with at least one of their source operands ready, or do not make use of two source registers to begin with. Our second scheme-tag memoizationavoids driving the upper portion of the tags, if those bits did not change their values from what was driven on the same tag bus during the most recent broadcast. While instruction packing results in the reduced length of the tag buses, tag memoization reduced the number of tag lines that need to be driven. We evaluate our designs using detailed microarchitectural simulations of the SPEC 2000 benchmarks and the SPICE simulations of the issue queue layouts.

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Out-of-Order Commit Processors

Abstract: Modern

Cited by 106 publications

References 23 publications

A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions

A Flexible Heterogeneous Multi-Core Architecture

Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization

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