Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems

Claus, Christopher; Ahmed, Rehan; Altenried, Florian; Stechele, Walter

doi:10.1007/978-3-642-12133-3_8

Cited by 40 publications

(22 citation statements)

References 8 publications

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“…Presently, this block may achieve 250 MHz ICAP overclocking if combined with a fast link to an external memory as demonstrated also by other authors in [3], [4].…”

Section: Introductionmentioning

confidence: 54%

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Salvador

Otero

Mora

et al. 2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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This paper addresses the modelling and validation of an evolvable hardware architecture which can be mapped on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The adaptation capabilities of the architecture are exercised to validate its evolvability. The underlying proposal is the use of a library of reconfigurable components characterised by their partial bitstreams, which are used by the Evolutionary Algorithm to find a solution to a given task. Evolution of image noise filters is selected as the proof of concept application. Results show that computation speed of the resulting evolved circuit is higher than with the Virtual Reconfigurable Circuits approach, and this can be exploited on the evolution process by using dynamic reconfiguration.

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“…Presently, this block may achieve 250 MHz ICAP overclocking if combined with a fast link to an external memory as demonstrated also by other authors in [3], [4].…”

Section: Introductionmentioning

confidence: 54%

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Salvador

Otero

Mora

et al. 2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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“…Within the automotive domain, FPGAs have been proposed to accelerate computationally intensive real time vision-based driver assistance systems [14], [15]. AUTOSAR compliant ECU architectures on FPGAs have also been proposed [16], which can be extended to ECU-on-chip designs that tightly integrate network interfaces and computational cores.…”

Section: Related Workmentioning

confidence: 99%

Accelerated Artificial Neural Networks on FPGA for Fault Detection in Automotive Systems

Shreejith

Anshuman

Fahmy

2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…The limitations of the HWICAP are discussed in more detail in Abouelella et al [2010]. There is extensive academic research on improving the Xilinx-provided HWICAP modules [Liu et al 2009;Bhandari et al 2012;Claus et al 2010;Manet et al 2008]. These HWICAP designs exhibit significantly better performance and/or reduced area.…”

Section: Dcs Overheadmentioning

confidence: 99%

Identification of Dynamic Circuit Specialization Opportunities in RTL Code

Davidson

Vansteenkiste

Heyse

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

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Dynamic Circuit Specialization (DCS) optimizes a Field-Programmable Gate Array (FPGA) design by assuming a set of its input signals are constant for a reasonable amount of time, leading to a smaller and faster FPGA circuit. When the signals actually change, a new circuit is loaded into the FPGA through runtime reconfiguration. The signals the design is specialized for are called parameters. For certain designs, parameters can be selected so the DCS implementation is both smaller and faster than the original implementation. However, DCS also introduces an overhead that is difficult for the designer to take into account, making it hard to determine whether a design is improved by DCS or not. This article presents extensive results on a profiling methodology that analyses Register-Transfer Level (RTL) implementations of applications to check if DCS would be beneficial. It proposes to use the functional density as a measure for the area efficiency of an implementation, as this measure contains both the overhead and the gains of a DCS implementation. The first step of the methodology is to analyse the dynamic behaviour of signals in the design, to find good parameter candidates. The overhead of DCS is highly dependent on this dynamic behaviour. A second stage calculates the functional density for each candidate and compares it to the functional density of the original design. The profiling methodology resulted in three implementations of a profiling tool, the DCS-RTL profiler. The execution time, accuracy, and the quality of each implementation is assessed based on data from 10 RTL designs. All designs, except for the two 16-bit adaptable Finite Impulse Response (FIR) filters, are analysed in 1 hour or less.

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Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems

Cited by 40 publications

References 8 publications

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Accelerated Artificial Neural Networks on FPGA for Fault Detection in Automotive Systems

Identification of Dynamic Circuit Specialization Opportunities in RTL Code

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