Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support

Abstract

This paper addresses the modelling and validation of an evolvable hardware architecture which can be mapped on a 2D systolic structure implemented on commercial reconfigurable FPGAs. The adaptation capabilities of the architecture are exercised to validate its evolvability. The underlying proposal is the use of a library of reconfigurable components characterised by their partial bitstreams, which are used by the Evolutionary Algorithm to find a solution to a given task. Evolution of image noise filters is selected as the proof of concept application. Results show that computation speed of the resulting evolved circuit is higher than with the Virtual Reconfigurable Circuits approach, and this can be exploited on the evolution process by using dynamic reconfiguration.

Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

“…Table II shows the average SAE values obtained after 100 independent runs of the EA for a Lena image with salt and pepper noise levels of 5%, 10%, and 20% (Fig. 10), comparing the result of the current parallelized (1+1)-EA with the singlethreaded (1+8)-EA used in [5], both taking advantage of the 8 systolic arrays to accelerate the evolution. Both algorithms are run for 32 768 generations, evaluating a total of 262 144 candidate solutions, although intermediate results after 65 536 (1/4 of the evolution time) and 131 072 evaluations (1/2) are also shown.…”

“…Another topology which does not suffer this problem is the systolic array, first defined in [4], as a generic computing engine, and used as a reconfigurable fabric for implementing EH in [5]. It was originally intended for complex PE operations but it can be used with simpler PEs as well.…”

“…Bus macros present an alternative to Xilinx's partial reconfiguration flow, and are used in in [5] in conjunction with a systolic array topology. A bus macro is a circuit with fixed routing used for anchoring nets, making the inputs and outputs of partial circuits compatible.…”

“…This configuration allows a broad range of processing functions to be implemented. The current implementation uses the 16 functions used in [5], which are listed in table I, all of which can be implemented in the described circuit. multiplexers, so they are switched by reconfiguring the FPGA instead of changing an input signal.…”

“…(The resulting filter will not be specific to the training image and can be used with other images with similar noise type and levels, as shown in [5]. )…”