Towards provably-secure performance locking

Zaman, Monir; Sengupta, Aditi; Liu, Danqing; Sinanoglu, Ozgur; Makris, Yiorgos; Rajendran, Jeyavijayan

doi:10.23919/date.2018.8342269

Cited by 10 publications

(5 citation statements)

References 20 publications

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“…ObfusGEM integrates logic locked netlists within a cycle-accurate GEM5 model of a processor [71]. By running arbitrary workloads on this model and tracking the divergence between a locked and unlocked processor, the application-level impact of logic locking is quantified [72]. This provides a promising avenue to evaluate logic locking moving forward.…”

Section: Perspectives On Application-level Directionsmentioning

confidence: 99%

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking

Tan,

Karri,

Limaye

et al. 2020

Preprint

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Section: Perspectives On Application-level Directionsmentioning

confidence: 99%

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking

Tan,

Karri,

Limaye

et al. 2020

Preprint

Self Cite

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“…where (21) represents that the latest arrival time at g i should be stable t su before a rising clock edge. The earliest arrival time s gi should be larger than t h as shown in (22), so that the data can be latched by the flip-flop ff k1 reliably.…”

Section: Wave-pipelining Construction For Timingcamouflage+mentioning

confidence: 99%

“…Furthermore, logic locking can be performed at sequential level to prevent the circuit from entering working states without a valid key [21]. Recently, logic locking has been applied to protect parametric behavior of circuits, e.g., pipelined processors [22], GPUs [23] and analog circuits [24]. The method in [22] adds meaningless clock cycles to camouflage a design, where only correct keys allow a high timing performance.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, logic locking has been applied to protect parametric behavior of circuits, e.g., pipelined processors [22], GPUs [23] and analog circuits [24]. The method in [22] adds meaningless clock cycles to camouflage a design, where only correct keys allow a high timing performance. However, various attack methods, e.g., SAT attack [25], removal attack [26] and bypass attack [27] can potentially recognize the correct keys.…”

Section: Introductionmentioning

confidence: 99%

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TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing

Zhang

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of authentic chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme, where all combinational blocks function within one clock period, so that a netlist of combinational logic gates and flip-flops is sufficient to duplicate a design. In this paper, we propose to invalidate the assumption that a netlist completely represents the function of a circuit with unconventional timing. With the introduced wave-pipelining paths, attackers have to capture gate and interconnect delays during reverse engineering, or to test a huge number of combinational paths to identify the wave-pipelining paths. To hinder the test-based attack, we construct false paths with wave-pipelining to increase the counterfeiting challenge. Experimental results confirm that wavepipelining true paths and false paths can be constructed in benchmark circuits successfully with only a negligible cost, thus thwarting the potential attack techniques.

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“…Recent works have proposed parametric locking [30,[39][40][41]; the essence is to lock design parameters and profiles. For example, in [39], the key not only protects the functionality of the design but also its timing profile.…”

Section: Future Directions For Logic Lockingmentioning

confidence: 99%

Protect Your Chip Design Intellectual Property

Knechtel

Patnaik

Sinanoglu

2019

Proceedings of the International Conference on Omni-Layer Intelligent Systems

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The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work. CCS CONCEPTS• Security and privacy → Security in hardware;

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Towards provably-secure performance locking

Cited by 10 publications

References 20 publications

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking

TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing

Protect Your Chip Design Intellectual Property

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