Towards evolvable systems based on the Xilinx Zynq platform

Dobai, Roland; Sekanina, Lukáš

doi:10.1109/ices.2013.6613287

Cited by 34 publications

(20 citation statements)

References 16 publications

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“…The first GA variant, referred to as a canonical GA, uses the tournament-selection, uniform-crossover and mutation genetic operators. Initial studies on canonical GAs did not value mutation, and thus mutation did not often feature [16]. This is in direct contrast to the second GA variant, referred to as a 1 + λ GA.…”

Section: Introductionmentioning

confidence: 76%

“…Thus, dynamic evolution is used in Evolvable Hardware. Most research during the last 20 years deals with simple digital/analogue circuit synthesis [22], image filtering [16], and system refinements [23]. There is little evidence of real-world applications being implemented, and thus most research is still focussed on refining systems, and testing these refinements by evolving simple circuits such as adders and multipliers [17].…”

Section: Variety Of Researchmentioning

confidence: 99%

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Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

Smith¹,

Berg²

2015

SACJ

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This paper propose a Virtual-Field Programmable Gate Array (V-FPGA) architecture that allows direct access to its configuration bits to facilitate hardware evolution, thereby allowing any combinational or sequential digital circuit to be realized. By using the V-FPGA, this paper investigates two possible ways of making evolutionary hardware systems more scalable: by optimizing the system’s genetic algorithm (GA); and by decomposing the solution circuit into smaller, evolvable sub-circuits. GA optimization is done by: omitting a canonical GA’s crossover operator (i.e. by using a 1+λ algorithm); applying evolution constraints; and optimizing the fitness function. A noteworthy contribution this research has made is the in-depth analysis of the phenotypes’ CPs. Through analyzing the CPs, it has been shown that a great amount of insight can be gained into a phenotype’s fitness. We found that as the number of columns in the Cartesian Genetic Programming array increases, so the likelihood of an external output being placed in the column decreases. Furthermore, the number of used LEs per column also substantially decreases per added column. Finally, we demonstrated the evolution of a state-decomposed control circuit. It was shown that the evolution of each state’s sub-circuit was possible, and suggest that modular evolution can be a successful tool when dealing with scalability.

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Section: Introductionmentioning

confidence: 76%

Section: Variety Of Researchmentioning

confidence: 99%

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

Smith¹,

Berg²

2015

SACJ

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“…After each candidate solution has been evaluated, another population is established based on the current population by use of bio-inspired operators (e.g., selection, mutation, crossover). The evolution is stopped at some point when a predetermined condition (e.g., maximum number of generations, time of evolution) is met and the solution with the best fitness is proclaimed as the result of the evolution [Greenwood and Tyrrell 2006;Sekanina 2012]. …”

Section: Background and Related Workmentioning

confidence: 99%

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Dobai

Sekanina

2015

ACM Trans. Reconfigurable Technol. Syst.

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Field-programmable gate arrays (FPGAs) can be considered to be the most popular and successful platform for evolvable hardware. They allow one to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Virtual reconfiguration is based on the change of functionality by hardware components implemented on top of FPGA resources. Native reconfiguration changes the FPGA resources directly by means provided by the FPGA manufacturer. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all-programmable system-on-chip. The proposed architecture offers high flexibility in comparison with other evolvable hardware systems by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast evaluation of candidate solutions. The proposed architecture is evaluated by evolutionary design of switching image filters and edge detectors. The experimental results demonstrate advantages over the previous approaches considering the time required for evolution, area overhead, and flexibility. ACM Reference Format:Roland Dobai and Lukas Sekanina. 2015. Low-level flexible architecture with hybrid reconfiguration for evolvable hardware.

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“…This paper utilises the high compaction properties of DWT for the compression of ultrasonic radio frequency (RF) signals, maintaining very high data compression rate with the objective to extract key features of the signal such as intensity and arrival time with a high level of accuracy [16]. The Zynq processing system contains dual-core ARM Cortex-A9 processor, cache memories, on-chip memory, external memory interfaces, direct memory access (DMA) controller and input-output peripherals [17]. Zynq platform enables system-level differentiation, integration and flexibility through hardware, software and input/ output (I/O) programmability.…”

Section: Introductionmentioning

confidence: 99%

Hardware and software architectures for computationally efficient three‐dimensional ultrasonic data compression

Govindan

Wang

Ravi

et al. 2016

IET Circuits, Devices & Systems

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Ultrasonic industrial and medical imaging applications involve acquisition of large amount of volumetric data in real time. Therefore, data storage becomes critical in many current day applications which utilise ultrasound technology. Compressing the acquired data allows possessing minimal storage and also helps to rapidly transmit information to remote locations for expert analysis. The objective of this study is to design computationally efficient architectures for implementing discrete wavelet transform-based ultrasonic three-dimensional (3D) data compression algorithm on a reconfigurable ultrasonic system-on-chip (SoC) hardware platform. In this study, hardware and software architectures of the 3D ultrasonic compression algorithm are realised using Xilinx Zynq all programmable SoC. This study demonstrates that, compressing 33 MB of experimental ultrasonic 3D data into 0.42 MB (98.7% compression) requires only 84 ms for hardware architecture, and 1 min for software architecture, making both designs highly suitable for realtime ultrasonic imaging applications. Furthermore, the 3D compression is implemented by using Open Computing Language (OpenCL) targeted on Nvidia GT 750M graphical processing unit. OpenCL implementation of ultrasonic 3D compression algorithm completes the execution in <1 sec. This approach provides improved computational performance as that of hardware architecture, and comparable flexibility as that of software implementation.

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Towards evolvable systems based on the Xilinx Zynq platform

Cited by 34 publications

References 16 publications

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

Hardware Genetic Algorithm Optimization by Critical Path Analysis using a Custom VLSI Architecture

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Hardware and software architectures for computationally efficient three‐dimensional ultrasonic data compression

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