Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Abstract

Field-programmable gate arrays (FPGAs) can be considered to be the most popular and successful platform for evolvable hardware. They allow one to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Virtual reconfiguration is based on the change of functionality by hardware components implemented on top of FPGA resources. Native reconfiguration changes the FPGA resources directly by means provided by the FPGA manufacturer. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all-programmable system-on-chip. The proposed architecture offers high flexibility in comparison with other evolvable hardware systems by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast evaluation of candidate solutions. The proposed architecture is evaluated by evolutionary design of switching image filters and edge detectors. The experimental results demonstrate advantages over the previous approaches considering the time required for evolution, area overhead, and flexibility. ACM Reference Format:Roland Dobai and Lukas Sekanina. 2015. Low-level flexible architecture with hybrid reconfiguration for evolvable hardware.

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

“…A problem with this topology is that the multiplexers at the input of each PE use a high amount of resources. For example, while an 8-bit adder processing element only needs 8 LUTs in total in modern Xilinx FPGAs, a single 13:1 multiplexer as proposed in [7] (9 inputs + 4 PEs) requires 4 LUTs per output bit [46], 64 LUTs in total for 2 input multiplexers. Therefore, multiplexers alone would represent 89% of the resource usage for this topology.…”

“…-Hybrid VRC-DPR methods for CGP-based image filters using PCAP. Virtual reconfiguration using multiplexers (but adding flip-flops at the outputs to reduce delay impact) is used for PEs interconnection, while PE reconfiguration is done through: (i) [6] DPR using pre-synthesized partial bitstreams; (ii) [7] DPR-based LUT reconfiguration for approximate PEs by direct bitstream manipulation.…”

Hexarray: A Novel Self-Reconfigurable Hardware System

“…This method is fast since the delay only depends on the time consumed by switching between functions, but it is not space or power efficient. Moreover, in some applications, VRC may result in lowering the maximum operational frequency [84]. Most of the early EHW systems were VRC-based for three reasons: (1) VRC is a simple method to be implemented.…”

“…Sekanina's research team at Brno University of Technology, Czech Republic, have conducted considerable research in using systolic arrays in image processing applications [84,90,169,171,172,30]. The utilized system was a 2D array of medium-grained processing elements that were reconfigured using a DPR scheme, as shown in figure 4.4.…”

“…In a recent paper (in 2015), a VRC/DPR hybrid FPGA-based EHW system was proposed, which was the first attempt toward this goal [84]. This system, however, has many drawbacks.…”