Towards energy-proportional datacenter memory with mobile DRAM

Abstract

To increase datacenter energy efficiency, we need memory systems that keep pace with processor efficiency gains. Currently, servers use DDR3 memory, which is designed for high bandwidth but not for energy proportionality. A system using 20% of the peak DDR3 bandwidth consumes 2.3× the energy per bit compared to the energy consumed by a system with fully utilized memory bandwidth. Nevertheless, many datacenter applications stress memory capacity and latency but not memory bandwidth. In response, we architect server memory systems using mobile DRAM devices, trading peak bandwidth for lower energy consumption per bit and more efficient idle modes. We demonstrate 3-5× lower memory power, better proportionality, and negligible performance penalties for datacenter workloads.

Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs

“…For Blackfin core, we measured 280 mW in full-on mode (no memory traffic) on a comparable single core BF527 in 65 nm process. We assume LPDDR2 memory interface, consuming 40pJ per bit transfer [7] with 15pJ per bit for SDRAM off-chip memory access [2]. For the selected HW accelerators, we consider an equal power efficiency as measured for the corresponding PVP FB.…”

Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation

“…The n-bit prefetching is used to address the asymmetric bus frequencies between the I/O bus and the internal bus. As highlighted in Figure 1, the data frequency on I/O bus is 1.6GHz (double data rate with 800MHz clock) while the internal bus only runs at 200MHz (single data rate) 5 . Since data bandwidth is calculated as the product of data width and data frequency (as shown by Equation 1), 128b data is fetched at each time to provide the same bandwidth as the I/O bus requires.…”

“…For example, prior work has demonstrated that DRAM can consume significant amount of power (sometimes more than 25% of the total power in a datacenter) [3,4,5,6,7]. As a result, how to improve the power efficiency of DRAM is one of the major challenges in the memory architecture design.…”

“…In DRAM, 8-bit prefetching in fact determines the internal data fetching primitives and the corresponding burst length 5. The internal bus can run faster with narrower bus width.…”

Exploring high-performance and energy proportional interface for phase change memory systems

“…The original LPDDR2 is proposed to become the technology of choice for embedded and mobile applications thanks to its low-power characteristics. Recently, [15] leverages LPDDR2 based DRAM in data centers. It is able to save a significant proportion of power (over 50%) under similar device density and performance conditions, which mainly comes from the reduced working voltage (1.2V) and the shrunken pin count.…”