2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA) 2014
DOI: 10.1109/isca.2014.6853217
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Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation

Abstract: DRAM memory is a major contributor for the total power consumption in modern computing systems. Consequently, power reduction for DRAM memory is critical to improve system-level power efficiency. Fine-grained DRAM architecture [1,2] has been proposed to reduce the activation/precharge power. However, those prior work either incurs significant performance degradation or introduces large area overhead. In this paper, we propose a novel memory architecture Half-DRAM, in which the DRAM array is reorganized to enab… Show more

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Cited by 47 publications
(54 citation statements)
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References 29 publications
(49 reference statements)
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“…This enables multiple rows in different sub-array within a bank to remain to be activated for the purpose of overlapping of latency. Other works [5,32] also enable multiple rows to be activated in a bank by activating only a portion of entire row. A patent [11] of IBM suggested a latched row decoder which activates multiple wordlines in order to reduce test time for defective-cell detection.…”
Section: Related Workmentioning
confidence: 99%
“…This enables multiple rows in different sub-array within a bank to remain to be activated for the purpose of overlapping of latency. Other works [5,32] also enable multiple rows to be activated in a bank by activating only a portion of entire row. A patent [11] of IBM suggested a latched row decoder which activates multiple wordlines in order to reduce test time for defective-cell detection.…”
Section: Related Workmentioning
confidence: 99%
“…Commodity DDR3 (2007) [14]; DDR4 (2012) [18] Low-Power LPDDR3 (2012) [17]; LPDDR4 (2014) [20] Graphics GDDR5 (2009) [15] Performance eDRAM [28], [32]; RLDRAM3 (2011) [29] 3D-Stacked WIO (2011) [16]; WIO2 (2014) [21]; MCDRAM (2015) [13]; HBM (2013) [19]; HMC1.0 (2013) [10]; HMC1.1 (2014) [11] Academic SBA/SSA (2010) [38]; Staged Reads (2012) [8]; RAIDR (2012) [27]; SALP (2012) [24]; TL-DRAM (2013) [26]; RowClone (2013) [37]; Half-DRAM (2014) [39]; Row-Buffer Decoupling (2014) [33]; SARP (2014) [6]; AL-DRAM (2015) [25] At the forefront of such innovations should be DRAM simulators, the software tool with which to evaluate the strengths and weaknesses of each new proposal. However, DRAM simulators have been lagging behind the rapid-fire changes to DRAM.…”
Section: Segment Dram Standards and Architecturesmentioning
confidence: 99%
“…However, PCM suffers from limited write operations and higher write energy. Fine-grained DRAM structures are also proposed to reduce the activate/precharge power by shrinking the width of each bank [10,11,12,13]. They may lead to lower row buffer hit rates due to the narrower row size, but better bank-level parallelism.…”
Section: Related Workmentioning
confidence: 99%