Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation

Zhang, Tao; Chen, Ke; Xu, Cong; Sun, Guangyu; Wang, Tao; Xie, Yuan

doi:10.1109/isca.2014.6853217

Cited by 47 publications

(54 citation statements)

References 29 publications

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“…This enables multiple rows in different sub-array within a bank to remain to be activated for the purpose of overlapping of latency. Other works [5,32] also enable multiple rows to be activated in a bank by activating only a portion of entire row. A patent [11] of IBM suggested a latched row decoder which activates multiple wordlines in order to reduce test time for defective-cell detection.…”

Section: Related Workmentioning

confidence: 99%

Multiple clone row DRAM

Choi

Shin

Jang

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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Several previous works have changed DRAM bank structure to reduce memory access latency and have shown performance improvement. However, changes in the area-optimized DRAM bank can incur large area-overhead. To solve this problem, we propose Multiple Clone Row DRAM (MCR-DRAM), which uses existing DRAM bank structure without any modification.Our key idea is Multiple Clone Row (MCR), in which multiple rows are simultaneously turned on or off to consist of a logically single row. MCR provides two advantages which enable our low-latency mechanisms (Early-Access, Early-Precharge and Fast-Refresh). First, MCR increases the speed of the sensing process by increasing the number of sensed-cells. Thus, it enables a READ/WRITE command to an MCR to be issued earlier than possible for a normal row (Early-Access). Second, DRAM cells in an MCR exhibit more frequent refreshes without additional REFRESH commands, thereby reducing the amount of charge leakage during the refresh interval for the identical cell. The reduced amount of charge leakage enables a PRECHARGE command to be served before the activatedcells are fully restored (Early-Precharge) and a REFRESH operation to be completed before the refreshed-cells are fully restored (Fast-Refresh).Even though MCR-DRAM sacrifices memory capacity for low-latency, it can be dynamically reconfigured from lowlatency to full-capacity DRAM. MCR-DRAM improves both performance and energy efficiency for both single-core and multi-core systems.

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Section: Related Workmentioning

confidence: 99%

Multiple clone row DRAM

Choi

Shin

Jang

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

View full text Add to dashboard Cite

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“…Commodity DDR3 (2007) [14]; DDR4 (2012) [18] Low-Power LPDDR3 (2012) [17]; LPDDR4 (2014) [20] Graphics GDDR5 (2009) [15] Performance eDRAM [28], [32]; RLDRAM3 (2011) [29] 3D-Stacked WIO (2011) [16]; WIO2 (2014) [21]; MCDRAM (2015) [13]; HBM (2013) [19]; HMC1.0 (2013) [10]; HMC1.1 (2014) [11] Academic SBA/SSA (2010) [38]; Staged Reads (2012) [8]; RAIDR (2012) [27]; SALP (2012) [24]; TL-DRAM (2013) [26]; RowClone (2013) [37]; Half-DRAM (2014) [39]; Row-Buffer Decoupling (2014) [33]; SARP (2014) [6]; AL-DRAM (2015) [25] At the forefront of such innovations should be DRAM simulators, the software tool with which to evaluate the strengths and weaknesses of each new proposal. However, DRAM simulators have been lagging behind the rapid-fire changes to DRAM.…”

Section: Segment Dram Standards and Architecturesmentioning

confidence: 99%

Ramulator: A Fast and Extensible DRAM Simulator

Kim

Yang

Mutlu

2016

IEEE Comput. Arch. Lett.

464

228

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Abstract-Recently, both industry and academia have proposed many different roadmaps for the future of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which can be easily modified to judge the merits of today's DRAM standards as well as those of tomorrow. In this paper, we present Ramulator, a fast and cycle-accurate DRAM simulator that is built from the ground up for extensibility. Unlike existing simulators, Ramulator is based on a generalized template for modeling a DRAM system, which is only later infused with the specific details of a DRAM standard. Thanks to such a decoupled and modular design, Ramulator is able to provide out-of-the-box support for a wide array of DRAM standards: DDR3/4, LPDDR3/4, GDDR5, WIO1/2, HBM, as well as some academic proposals (SALP, AL-DRAM, TL-DRAM, RowClone, and SARP). Importantly, Ramulator does not sacrifice simulation speed to gain extensibility: according to our evaluations, Ramulator is 2.5× faster than the next fastest simulator. Ramulator is released under the permissive BSD license.

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“…However, PCM suffers from limited write operations and higher write energy. Fine-grained DRAM structures are also proposed to reduce the activate/precharge power by shrinking the width of each bank [10,11,12,13]. They may lead to lower row buffer hit rates due to the narrower row size, but better bank-level parallelism.…”

Section: Related Workmentioning

confidence: 99%

Exploring new features of high-bandwidth memory for GPUs

Song

Jiang

et al. 2016

IEICE Electron. Express

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Due to the off-chip I/O pin and power constraints of GDDR5, HBM has been proposed to provide higher bandwidth and lower power consumption for GPUs. In this paper, we first provide detailed comparison between HBM and GDDR5 and expose two unique features of HBM: dualcommand and pseudo channel mode. Second, we analyze the effectiveness of these two features and show that neither notably contributes to performance. However, by combining pseudo channel mode with cache architecture supporting fine-grained cache-line management such as Amoeba cache, we achieve high effciency for applications with irregular memory requests. Our experiment demonstrates that compared with Amoeba caches with legacy mode, Amoeba cache with pseudo channel mode improves GPU performance by 25% and reduces HBM energy consumption by 15%.

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Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation

Cited by 47 publications

References 29 publications

Multiple clone row DRAM

Multiple clone row DRAM

Ramulator: A Fast and Extensible DRAM Simulator

Exploring new features of high-bandwidth memory for GPUs

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