Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture

Abstract

This paper presents an efficient real-time variable block size motion estimation architecture. The proposed architecture provides motion vectors for each 16 16 block and its 40 sub-blocks. The proposed architecture is a single-instruction multiple-data architecture integrated with embedded SRAMs on one chip. The architecture has been prototyped using Xilinx Virtex-4 XC4VSX35-10 field-programmable gate array. It processes 30-CIF fps using 71-MHz clock frequency. Its maximum clock frequency is 187.7 MHz and the maximum throughput is 20 4CIF fps. The prototyped architecture has 175 k gates and 18 kbits embedded SRAM.Index Terms-H.264, single-instruction multiple-data (SIMD) architecture, variable block size motion estimation (VBSME).

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

“…In literature, several studies regarding the SIMD optimization of video-coding applications are available [7][8][9][10][11]. The scope driving these studies is the achievement of the maximum performance, adopting measures in order to reduce the known bottlenecks.…”

Dual-core motion estimation processor

“…Be sides, they do not ensure the optimum result. Consequently, the FSBMA is usually used in the hardware implementation of ME, because of its simplicity, regularity, and optimum result [4] [5].…”

IP Based Configurable SIMD Massively Parallel SoC

“…They can be partitioned into hardware specific solutions [11], [12], or reconfigurable solutions [7]. However, they are hard to implement and they are optimized for specific applications.…”