IP Based Configurable SIMD Massively Parallel SoC

Baklouti, Mouna; Abid, Mohamed; Marquet, Philippe; Dekeyser, Jean-Luc

doi:10.1109/fpl.2010.57

Cited by 6 publications

(2 citation statements)

References 10 publications

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“…The mppSoC system can be customized to target diverse applications [18]. Our design approach aims to define an mppSoC configuration adapted to a given application.…”

Section: B a Parametric Architecture For Data-parallel Applicationsmentioning

confidence: 99%

Extending MARTE to Support the Specification and the Generation of Data Intensive Applications for Massively Parallel SoC

Ammar

Baklouti

Abid

2012

2012 15th Euromicro Conference on Digital System Design

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The presented work proposes a MARTE (Modeling and Analysis of Real-Time and Embedded systems) extension for the specification of data-parallel applications designed to be executed on mppSoC, a massively parallel System-on-Chip. These applications can be clearly specified and generated using our transformation chain, which is automated and is a combination of contributions in different domains such as Model-Driven Engineering, MARTE modeling and automatic code generation. The modeling methodology as well as the generation process are validated by an image processing application example.

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“…The mppSoC system can be customized to target diverse applications [18]. Our design approach aims to define an mppSoC configuration adapted to a given application.…”

Section: B a Parametric Architecture For Data-parallel Applicationsmentioning

confidence: 99%

Extending MARTE to Support the Specification and the Generation of Data Intensive Applications for Massively Parallel SoC

Ammar

Baklouti

Abid

2012

2012 15th Euromicro Conference on Digital System Design

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“…With the evolutions of system design, silicon integration technology and demands of applications on the computing power, a SIMD machine in single chip system integration seems important to consider and verify the feasibility of massively parallel models on chip dedicated to complex applications. Thus, a massively parallel SIMD processing Systemon-Chip named mppSoC [13], [14] is defined since 2010. This system is generic, parametric in order to be adapted to the application requirements.…”

Section: Related Workmentioning

confidence: 99%

Broadcast with mask on a massively parallel processing on a chip

Krichene

Baklouti

Abid

et al. 2012

2012 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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The delay of instructions broadcast has a significant impact on the performance of Single Instruction Multiple Data (SIMD) architecture. This is especially true for massively parallel processing Systems-on-Chip (mppSoC), where the processing stage and that of setting up the communication mechanism need several clock periods. Subnetting is the strategy used to partition a single physical network into more than one smaller logical sub-networks (subnets). This technique better controls the broadcast instructions domain and the data traffic between network nodes. Furthermore, it allows to separate synchronous communications from asynchronous processing which maintains reliable communications and rapid processing through parallel processors. This paper describes the design of a communication model called broadcast with mask. This model is dedicated to mppSoC architecture with a huge number of processor elements because it maintains performances even when the number of processors increases. Simulation results and an FPGA implementation validate our approach.

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