Synchronous Communication-Based Many-Core SoC

Baklouti, Mouna; Krichene, Hana; Abid, Mohamed

doi:10.1007/s13369-016-2373-2

Cited by 1 publication

(2 citation statements)

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“…This SoC architecture uses the ARM Cortex-A15 multicore processor with advanced microcontroller bus architecture (AMBA) [15]. There are two different processing cores included in this SoC, namely, ARM Cortex A15, also known as a general purpose multiprocessor (GPMCP), and digital signal processing (DSP) processor [12]. These GPMCP and DSP processors are coupled with the memory controller core, enabling them to collaborate with other external flash memory, and system memory with the help of a high-performance AMBA advanced high-performance bus (AHB).…”

Section: Soc Architecture With Multiprocessing Unitsmentioning

confidence: 99%

“…In recent times, multiprocessor systems have been drastically used to improve power performance compared to single processor systems in desktop segments. It caused the extensive application of multiple processor SoC cores, known as multiprocessor SoCs (MPSoCs) [11,12]. These MPSoC cores are commonly available in the latest smartphone and other gaming devices.…”

Section: Introductionmentioning

confidence: 99%

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A Smart Memory Controller for System on Chip‐Based Devices

Ahmed

Aloufi

2022

Journal of Nanomaterials

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This research paper deals with a system-on-chip (SoC) architecture design where multiple processors are inbuilt with other blocks of memory and control logic developed by nanomaterials. The multiprocessing-based SoC architecture is commonly used in the latest electronic devices such as smartphones, tablets, and smart wristwatches with large memory sizes. The data handing in these highly memory-dense devices is a critical task, and it needs special attention for the smooth operation of the device. This research proposed a smart controller to exchange data between various processors and input-output devices to tackle this challenge. A proposed controller block controls the data flow between memory and different SoC components and processors. A memory access controller (MAC) is presented in this research study to manage and accelerate data transmission speed and reduce the processors’ activity for SoC-based devices. The proposed MAC will integrate into the SoC with multiprocessing units, including gaming processors, at minimum hardware overhead and low power consumption. It improves the memory accessing efficiency and reduces the processors’ activity of a system. As a result, the system’s performance and power consumption improve at an acceptable level compared with the other conventional methods. This research is aimed at enhancing the performance of any SoC-based device where multiprocessing engines are inbuilt and flexible enough to serve various SoCs.

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Section: Soc Architecture With Multiprocessing Unitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%