An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

Abstract

The optimization process of a H.264/AVC encoder on three different architectures is presented. The architectures are multiand singlecore and SIMD instruction sets have different vector registers size. The need of code optimization is fundamental when addressing HD resolutions with real-time constraints. The encoder is subdivided in functional modules in order to better understand where the optimization is a key factor and to evaluate in details the performance improvement. Common issues in both partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented for all the architectures. Besides showing efficient video encoder implementations, one of the main purposes of this paper is to discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application performance. Results about the achieved speedup are provided in order to compare the different implementations and evaluate the more suitable solutions for present and next generation video-coding algorithms.

An optimized software implementation of the HEVC/H.265 video decoder

“…NEON supports only vertical SIMD (operation among different vectors), and do not provide a useful support for horizontal SIMD: the operations between elements inside the same vector are limited to three instructions (add, min and max) that only operates between adjacent pairs of elements. This can be considered a limitation of NEON ISA because horizontal SIMD can be well exploited in video coding operations like Sum of Absolute Difference (SAD) [18]. Load and store instructions are flexible and provide access to multiple N-element structures, with N from 1 to 4.…”

An optimized SIMD implementation of the HEVC/H.265 video decoder

“…NEON supports only vertical SIMD (operation among different vectors), and do not provide a useful support for horizontal SIMD: the operations between elements inside the same vector are limited to three instructions (add, min and max) that only operates between adjacent pairs of elements. This can be considered a limitation of NEON ISA because horizontal SIMD can be well exploited in video coding operations like Sum of Absolute Difference (SAD) [20]. Load and store instructions are flexible and provide access to multiple N-element structures, with N from 1 to 4.…”