An optimized software implementation of the HEVC/H.265 video decoder

Abstract

In this paper an optimized implementation of the HEVC video decoder is shown. The solutions developed to support the new features of HEVC are shown together with the achieved performance. The HEVC decoder complexity has been evaluated and the most demanding modules have been optimized exploiting SIMD instructions. Even though the here described concepts have a general value, the effectiveness of the proposed solutions has been verified on the ARM architecture. The selected architecture is ARM Cortex A9 with NEON SIMD extension. We will demonstrate that the resulting real-time HEVC software decoder can decode 720p (1280x720) streams at 30 frames per second on a single core ARMv7 at 1.2 GHz.

Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors

“…In [6], the authors use SIMD instructions to accelerate all major modules of an HEVC decoder, obtaining speed-ups of up to 5× on mobile and desktop platforms, to deliver 1080p real-time decoding. Similarly, the authors of [11,19,2] report 720p real-time decoding on an ARM Cortex-A9 platform and 1080p real-time decoding on an Intel platform. Although all these works leverage SIMD optimizations on energy-constrained devices, none of them analyzes the impact of this type of optimizations in terms of energy consumption.…”

Aportaciones metodológicas para el diseño de descodificadores de vídeo de última generación sobre plataformas Multi-DSP

“…In a similar sense other researchers present works where a real-time decoding rate is achieved using two ARM Cortex A-9 cores with the same images resolution, [DSY + 14] and [BLRP14].…”

“…En [BLRP14] investigadores de la Universidad de Genoa realizan una implementación del descodificador HEVC con optimizaciones SIMD sobre un ARM Cortex A9 con dos núcleos. En los resultados presentados se consiguen, en el mejor de los casos, tasas de descodificación de hasta 73 FPS para una secuencia con una resolución de 1280x720 píxeles.…”