Towards a mixed NoC/AFDX architecture for avionics applications

Abdallah, Laure; Scharbarg, Jean‐Luc; Fraboul, Christian

doi:10.1109/wfcs.2017.7991950

Cited by 3 publications

(9 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Objective function (3) means that the applications should be stored in a minimum of lines of table N defined by equation (2). Constraints (4) impose that the capacity of each line defined by equation 1is not exceeded while constraints (5) ensure that all the applications are packed.…”

Section: Formulationmentioning

confidence: 99%

“…These rules are based on the principle of allocating the tasks which generate perpendicular communications on the path of the core-to-I/O flows. • ex_Map IO [2]: this approach is an extension of Map IO in order to minimize the delay of outgoing I/O flows on the NoC (such as d, d1 and d2 in Figure 3). Several mapping rules have been defined.…”

Section: Mapping Applications Into the Manycorementioning

confidence: 99%

“…Second, the Ethernet controller can be busy, transmitting another frame. [2] proposes a mapping strategy which minimizes the first factor, i.e. the variation of this NoC delay.…”

Section: Introductionmentioning

confidence: 99%

“…The new approach is described in Section 4. Section 5 shows the proposed scheduling solution on a case study and give some results compared to the distributed solution of [2]. Finally, Section 6 concludes with some future works.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture

Mouysset

Scharbarg

Fraboul

2018

Proceedings of the 26th International Conference on Real-Time Networks and Systems

Self Cite

View full text Add to dashboard Cite

Current avionics architecture are based on an avionics full duplex switched Ethernet network (AFDX) that interconnects end systems. Avionics functions exchange data through Virtual Links (VLs), which are static flows with bounded bandwidth. The jitter for each VL at AFDX entrance has to be less than 500 µs. This constraint is met, thanks to end system scheduling. The interconnection of many-cores by an AFDX backbone is envisioned for future avionics architecture. The principle is to distribute avionics functions on these many-cores. Many-cores are based on simple cores interconnected by a Network-on-Chip (NoC). The allocation of functions on the available cores as well as the transmission of flows on the NoC has to be performed in such a way that the jitter for each VL at AFDX entrance is still less than 500 µs. A first solution has been proposed, where each function manages the transmission of its VLs. The idea of this solution is to distribute functions on each many-core in order to minimize contentions for VLs which concern functions allocated on different many-cores. In this paper, we consider that VL transmissions are managed by a single task in each many-core. We propose to construct a scheduling table executed by this task using an Integer Linear Program. The access to the Ethernet interface is then only allowed to one VL leading to a significant reduction of the jitter.

show abstract

Section: Formulationmentioning

confidence: 99%

Section: Mapping Applications Into the Manycorementioning

confidence: 99%

“…Second, the Ethernet controller can be busy, transmitting another frame. [2] proposes a mapping strategy which minimizes the first factor, i.e. the variation of this NoC delay.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture

Mouysset

Scharbarg

Fraboul

2018

Proceedings of the 26th International Conference on Real-Time Networks and Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…The authors of [2] extended the Map IO strategy. Several rules have been defined to minimize the delay of outgoing I/O flows on the NoC, i.e.…”

Section: Problem Statementmentioning

confidence: 99%

Reducing AFDX jitter in a mixed NoC/AFDX architecture

Abdallah¹,

Scharbarg²,

Fraboul³

2018

2018 14th IEEE International Workshop on Factory Communication Systems (WFCS)

Self Cite

View full text Add to dashboard Cite

Current avionics architecture are based on an avionics full duplex switched Ethernet network (AFDX) that interconnects end systems. Avionics functions exchange data through Virtual Links (VLs), which are static flows with bounded bandwidth. The jitter for each VL at AFDX entrance has to be less than 500 µs. This constraint is met, thanks to end system scheduling. The interconnection of many-cores by an AFDX backbone is envisionned for future avionics architecture. The principle is to distribute avionics functions on these manycores. Many-cores are based on simple cores interconnected by a Network-on-Chip (NoC). The allocation of functions on the available cores as well as the transmission of flows on the NoC has to be performed in such a way that the jitter for each VL at AFDX entrance is still less than 500 µs. A first solution has been proposed, where each function manages the transmission of its VLs. The idea of this solution is to distribute functions on each many-core in order to minimize contentions for VLs which concern functions allocated on different many-cores. In this paper, we consider that VL transmissions are managed by a single task in each many-core. We show on a preliminary case study that this solution significantly reduces VL jitter.

show abstract

Limiting over sampling to improve transmission schedulability in a mixed NoC/AFDX architecture

Mouysset

Scharbarg

2019

2019 24th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA)

Self Cite

View full text Add to dashboard Cite

Current avionics architecture are based on an avionics full duplex switched Ethernet network (AFDX) that interconnects end systems. Avionics functions exchange data through Virtual Links (VLs), which are static flows with bounded bandwidth. The jitter for each VL at AFDX entrance has to be less than 500µs. This constraint is met, thanks to end system scheduling. The interconnection of many-cores by an AFDX backbone is envisioned for future avionics architecture. The principle is to distribute avionics functions on these manycores. Many-cores are based on simple cores interconnected by a Network-on-Chip (NoC). The allocation of functions on the available cores as well as the transmission of flows on the NoC has to be performed in such a way that the jitter for each VL at AFDX entrance is still less than 500µs. A first solution has been proposed, where a single task in each manycore manages the transmission of the VLs. This task executes a scheduling table. The access to the Ethernet interface is then only allowed to one VL leading to a significant reduction of the jitter. By oversampling the VL transmissions in a minimum period, the waiting delays are also reduced. But this solution limits the number of VLs. In this paper, we propose to improve the transmission scheduling by relaxing constraint on the over sampling. A new scheduling table is constructed using an Integer Linear Program. This solution increases the number of VLs transmitted by the many-core and still reduces the waiting delays for the transmission of the VLs.

show abstract

Towards a mixed NoC/AFDX architecture for avionics applications

Cited by 3 publications

References 9 publications

Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture

Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture

Reducing AFDX jitter in a mixed NoC/AFDX architecture

Limiting over sampling to improve transmission schedulability in a mixed NoC/AFDX architecture

Contact Info

Product

Resources

About