Reducing AFDX jitter in a mixed NoC/AFDX architecture

Abstract

Current avionics architecture are based on an avionics full duplex switched Ethernet network (AFDX) that interconnects end systems. Avionics functions exchange data through Virtual Links (VLs), which are static flows with bounded bandwidth. The jitter for each VL at AFDX entrance has to be less than 500 µs. This constraint is met, thanks to end system scheduling. The interconnection of many-cores by an AFDX backbone is envisionned for future avionics architecture. The principle is to distribute avionics functions on these manycores. Many-cores are based on simple cores interconnected by a Network-on-Chip (NoC). The allocation of functions on the available cores as well as the transmission of flows on the NoC has to be performed in such a way that the jitter for each VL at AFDX entrance is still less than 500 µs. A first solution has been proposed, where each function manages the transmission of its VLs. The idea of this solution is to distribute functions on each many-core in order to minimize contentions for VLs which concern functions allocated on different many-cores. In this paper, we consider that VL transmissions are managed by a single task in each many-core. We show on a preliminary case study that this solution significantly reduces VL jitter.

Design and verification of avionics full duplex switched ethernet network data monitoring analyzer AFDX network data monitoring analyzer

“…In order to mathematically deal with the delay allowed by the terminal system in transmission, two limit cases are defined. For the first case, assume that the managed partition transmits evenly spaced data over a given VL and does not need to fragment the data [15] . Then, if the end system has no other data to process on the virtual link, the total allowable delay for a given VLi is:…”