No abstract

Many-core architectures are promising hardware to design real-time systems. However, the worst-case behavior of the Network-on-Chip (NoC) for both core-to-core and core-to-Input/Output 1 (I/O) communications of critical applications must be established. The mapping over the NoC of both critical and non-critical applications has an impact on the network contention these critical communications exhibit. So far, all existing mapping strategies have focused on core-to-core communications. However, many-cores in embedded real-time systems will be integrated within backbone Ethernet networks, as they mostly provide Ethernet controllers as I/O interfaces. In a previous work we have shown that Ethernet packets can be dropped due to an internal congestion in a Tilera-like NoC. In this work, we describe and evaluate a mapping strategy for such Tilera-like NoCs that minimizes the contention of core-to-I/O critical flows in order to solve this problem. Experimental results on real avionics applications show significant improvements of coreto-IO flows transmission delays, without significantly impacting transmission delays of core-to-core flows.

An heterogeneous network, where a switched-Ethernet backbone, as AFDX, interconnects several End Systems based on Network-On-Chip (NoC), is a promising candidate to build new avionics architecture. However, current avionics End System includes many functions, as performing a traffic shaping for each Virtual Link (VL) and scheduling the output frames in such a way the jitter on each VL is bounded. This paper describes how the NoC implements these functions in order to compute the worst-case traversal time (WCTT) of avionics frames on a NoC to reach the AFDX network. Besides, we illustrate the problem of guaranteeing a bounded jitter at the output of a NoC. We show that the existing mapping strategies present some limitations to reduce the congestion on the outgoing I/O flows (i.e. going from the NoC to the AFDX network) and so do not reduce the jitter on a given VL. We propose an extended mapping approach which considers the outgoing I/O flows. Experimental results on realistic avionics case studies show significant improvements of the jitter value.