Total Ionizing Dose Response and Annealing Behavior of Bulk nFinFETs With ON-State Bias Irradiation

Yang, Ling; Zhang, Qingzhu; Huang, Yunbo; Zheng, Zhongshan; Li, Bo; Li, Binhong; Zhang, Xingyao; Zhu, Huiping; Guo, Qi; Luo, Jiajun; Han, Zhewen

doi:10.1109/tns.2018.2827675

Cited by 25 publications

(8 citation statements)

References 23 publications

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“…It considers that the combination of holes in the oxide trap induced by the total dose irradiation and hot electrons reduces the positive charge in the oxide trap. The irradiation-induced interface state captures the hot electrons to form negative interface trap charges [12] . But, to the best of our knowledge, no studies have shown how total ionizing dose radiation affects HCI in 22 nm FinFETs.…”

Section: Introductionmentioning

confidence: 99%

The influence of total ionizing dose on the hot carrier injection of 22 nm bulk nFinFET

et al. 2020

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We investigate the hot carrier injection effect (HCI) and how X-ray radiation impacts the HCI of 22-nm nFinFETs as a function of device geometry and irradiation bias conditions in this paper. In the HCI test, the degradation of threshold voltage and saturation current decreases with the increase of fin number, which means that HCI weakens when the fin number increases. The reason is attributed to the coupling effect between fins. Moreover, irradiation is shown to weaken the degradation during the subsequent hot carrier test. The influence of irradiation on HCI is more obvious with ON bias than that of OFF bias and transmission gate bias. It is supposed that the Si–H bonds can be broken by irradiation before the HCI test, which is one reason for the irradiation influence on HCI. Besides, trapped charges are generated in the shallow trench isolation by the radiation, which could reduce the channel electric field, and then weaken the HCI.

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Section: Introductionmentioning

confidence: 99%

The influence of total ionizing dose on the hot carrier injection of 22 nm bulk nFinFET

et al. 2020

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“…The source and drain are connected to form a parasitic leakage path. Besides, maximum transconductance increase is due to the parasitic structures induced by trapped charges in STI [21]. Therefore, similar to the total ionizing dose effect [4], this phenomenon is more easily to be observed in devices with smaller gate widths, and is barely observed in wide devices.…”

Section: Effects Of Heavy Ion Irradiationmentioning

confidence: 95%

Statistical analysis on the effects of heavy ion irradiation on 65 nm bulk silicon MOS devices

Ren¹,

An²,

Li³

et al. 2019

Semicond. Sci. Technol.

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In this paper, the effect of heavy ion irradiation on 65 nm bulk silicon MOS devices is experimentally investigated. Different performance degradation behaviour is observed due to the intrinsic random incident of heavy ions. After irradiation, the threshold voltage (V th ) shifts negatively and the largest V th shift is 54 mV. The drain induced barrier lowing (DIBL) effect deteriorates and DIBL increases by more than 30 mV V −1 . The variation of maximum transconductance (G m ) is up to 30%. The off-state leakage current (I off ) increases by several times, up to one order of magnitude. These performance degradation is attributed to the displacement damage in the active region, interface states at gate oxide interface and trapped charges in shallow trench isolation (STI) induced by micro-dose effect. Moreover, statistical analysis on the geometry dependence is firstly demonstrated. The average value of V th shift, DIBL shift, and I off degradation increase with the decrease of gate width. Finally, the influence of technology downscaling from deep-submicron to nanoscale on the heavy ion irradiation effect is statistically analyzed. Four technology nodes (65 nm, 90 nm, 0.18 μm and 0.25 μm) are chosen for comparison. The results indicates that the V th shift and DIBL shift increase with the technology downscaling. The I off degradation is strongly correlated with the trapped charge in STI caused by micro-dose effect. The results are helpful to further understand the single event effects of nanoscale bulk silicon MOS devices and may provide guideline for radiation-hardened design.

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“…Beyond the 22-nm node, these changes in conventional Si MOSFET planar bulk architecture were insufficient to achieve the performance metrics indicated by the ITRS specifications. Therefore, researchers have been exploring alternative advanced transistor architectures such as multigate, GAA [ 9 ], fully depleted silicon-on-insulator (FDSOI) [ 10 , 11 ] and fin field effect transistor (FinFET) [ 12 , 13 ] devices. Apart from process integration problems, another major challenge is to monitor process variations for such small-geometry devices so that the statistical variations of system parameters, such as I on and V th , are limited within acceptable limits.…”

Section: Introductionmentioning

confidence: 99%

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

et al. 2021

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At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

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Total Ionizing Dose Response and Annealing Behavior of Bulk nFinFETs With ON-State Bias Irradiation

Cited by 25 publications

References 23 publications

The influence of total ionizing dose on the hot carrier injection of 22 nm bulk nFinFET

The influence of total ionizing dose on the hot carrier injection of 22 nm bulk nFinFET

Statistical analysis on the effects of heavy ion irradiation on 65 nm bulk silicon MOS devices

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length

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