“…However, despite the SEE immunity of their configuration memory, their Floating Gate (FG) switches and CMOS logic gates are susceptible to both effects of the Total Ioninzing Dose (TID) and the Single Event Effects (SEE). For TID effects, the primary issue is the radiation-induced charge loss in the floating gate [Snyder et al, 1989, Cellere et al, 2004, Wang et al, 2004, Guertin et al, 2006, resulting in the change of the FPGA electrical performances (maximum speed, current, etc.). While for SEE, the primary concern resides in the upset of its registers (state of the flip-flop) due to a particle hit, resulting in the disruption of the normal operation of the FPGA-design [Rezgui et al, 2007a[Rezgui et al, & 2007b.…”