Total ionizing dose effects in multiple-gate field-effect transistor

Gaillardin, M.; Marcandella, Claude; Martinez, M.; Paillet, Philippe; Duhamel, Olivier; Richard, Nicolas

doi:10.1088/1361-6641/aa6c02

Cited by 15 publications

(8 citation statements)

References 79 publications

(141 reference statements)

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“…As a result, traps are formed at the silicon-oxide interface, due to the release of radiolytic hydrogen and the formation of dangling bonds [4]. The interface traps mainly manifest as negatively charged traps in n-type devices, while the opposite is true for p-type devices [25][26][27]. Figure 3 depicts the method used to assess TID effects in this work; a similar method has successfully been applied to LDMOS devices [4].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Evaluation of total-ionizing-dose effects on reconfigurable field effect transistors and SRAM circuits

Shao¹,

Li²,

Liu³

et al. 2021

Semicond. Sci. Technol.

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For the first time, this paper presents a qualitative analysis of the total-ionizing-dose effects on reconfigurable field effect transistors (RFETs) and the corresponding static random-access memory (SRAM) circuits based on 3D technology computer aided design simulations. The effects of various electrical biases and geometric parameters are investigated in detail. For nand p-type programs, the threshold voltages (V TH ) respectively decrease by 83 mV and increase by 57 mV after 40 Mrad (Si) of irradiation. Radiation-induced oxide trap charges in the spacer region near the source side are shown to mainly dominate the performance degradation in RFETs. The control gate voltage (V CG ) and spacer length on the source side L S_Spacer are shown to have a significant influence on the total-ionizing-dose response, and a shorter L S_Spacer presents a stronger total-dose tolerance. When the RFETs in SRAMs suffer from a degraded V TH , the SRAM's read static noise margin declines by 51.3 mV after 40 Mrad (Si) of irradiation. This work provides a radiation hardening foundation for the application of RFET technology in future extreme-environment electronics applications.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Evaluation of total-ionizing-dose effects on reconfigurable field effect transistors and SRAM circuits

Shao¹,

Li²,

Liu³

et al. 2021

Semicond. Sci. Technol.

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“…Thorough reviews are provided in [42] and [43]. Here, we stress on the role that the distribution of trapped charge in the field oxide plays for the emergence of this complexity.…”

Section: Finfets and Other Multigate Architecturesmentioning

confidence: 99%

“…In SOI FinFETs, the electrostatic potential of the gate reduces when the gate length decreases, and therefore charges trapped in the BOX dominate the TID response. Therefore, for gate lengths less than 40 nm, it is advised to use an SOI structure that gives more control over the channel, such as the gate-allaround (GAA) described in Section V [43].…”

Section: Finfets and Other Multigate Architecturesmentioning

confidence: 99%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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-From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.Index Terms-2-D semiconductor, carbon, CMOS, deep submicrometer, FinFET, graphene, MoS2, resistive random access memory (RRAM), silicon-on-insulator (SOI), thin film, total ionizing dose (TID), ultrathin buried oxide (UTBOX).

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“…Although the LTPS TFTs show great electrical properties without radiation state, noticeable decay and electrical instability are observed when the devices are irradiated by xrays. In the aspect of characteristics, some research reported the threshold voltage (V th ) shift and mobility change after xray irradiation [8][9][10]. While in the aspect of response time, many related research is studied.…”

Section: Introductionmentioning

confidence: 99%

The time response for the low-temperature poly-silicon thin-film transistors to x-ray irradiation pulse

Tai¹,

Yeh²,

Chen³

et al. 2021

Semicond. Sci. Technol.

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In this study, the time response behavior of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) to x-ray irradiation pulses with different frequencies is analyzed. The formulas for the time response of excited and recovery behaviors are proposed for possible use in circuit performance enhancement in real x-ray irradiation situations. The predicted and measured results fit fairly well, which is important in the development of x-ray image sensors using LTPS TFTs.

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Total ionizing dose effects in multiple-gate field-effect transistor

Cited by 15 publications

References 79 publications

Evaluation of total-ionizing-dose effects on reconfigurable field effect transistors and SRAM circuits

Evaluation of total-ionizing-dose effects on reconfigurable field effect transistors and SRAM circuits

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

The time response for the low-temperature poly-silicon thin-film transistors to x-ray irradiation pulse

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