Total dose failures in advanced electronics from single ions

Abstract

Hard errors from single heavy ions have been reported in advanced commercial CMOS memories. We examine the physical interactions of ions with MOS gate oxides-charge generation, recombination, transport and trapping. We also consider device and circuit characteristics. We conclude that hard errors from single ions are to be expected, and should not be considered surprising.

The shape of heavy ion upset cross section curves (SRAMs)

“…However, for some memories the critical charge distribution may be similar to the transistor threshold voltage distribution, which is almost always measured during the fabrication process. Studies have shown that the variation in transistor threshold voltages across a single die is usually controlled by the microscopic variation in the threshold adjust implant [12]. Since the average number of implanted ions per transistor is rather large (on the order of loo0 [12]), the threshold voltage distribution is expected to be approximately Gaussian.…”

“…Studies have shown that the variation in transistor threshold voltages across a single die is usually controlled by the microscopic variation in the threshold adjust implant [12]. Since the average number of implanted ions per transistor is rather large (on the order of loo0 [12]), the threshold voltage distribution is expected to be approximately Gaussian. Thus, in the following calculation, the critical charge probability density is taken as where s% and e7 are the standard deviation and average critical charge of the memory.…”

Cosmic and terrestrial single-event radiation effects in dynamic random access memories

“…If the relative size of the ion track and the device gate region are comparable, a significant total-dose device response can be generated-a large threshold voltage shift. This can lead to device failure and stuck bits (hard errors) in scaled DRAM structures, as predicted by Oldham et al [38] and observed by Swift et al in 4-Mb DRAM's [39]. The implications are important, especially when analyzing the effectiveness of EDAC in space environments, a subject discussed in Section VIII.…”

“…A last error mechanism, single-event hard errors, is a newly discovered upset response to heavy ions that may have significant implications in memory scaling and DRAM use in space applications [38], [39]. This microdose circuit effect, first observed in resistive-load SRAM devices L381, [401, [411, is the deposition of oxide charge by a heavy ion within the gate region of a submicron MOS device.…”

Effects of heavy ion exposure on nanocrystal nonvolatile memory

“…This mechanism has been described most completely for normal gate oxides [9,10]. However, Cellere et al [A reported that the negative charge lost off floating gate devices irradiated with heavy ions was far greater than the amount of positive charge deposited by an ion.…”