Total dose effects of 28nm FD-SOI CMOS transistors

Kuang, Yong Kang; Bu, Jianhui; Li, Bo; Gao, Linchun; Liang, Chunping; Luo, Zheng-sheng

doi:10.1109/s3s.2018.8640197

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…In recent years, many scholars have conducted extensive research on the TID effects of nanoscale electronic devices, including 28 nm bulk transistors, 28 nm FD-SOI transistors, and 20 nm UTB-FDSOI devices [8][9][10][11]. Different from conventional planar bulk devices, SOI devices feature an insulating buried oxide (BOX) layer.…”

Section: Introductionmentioning

confidence: 99%

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Yan

et al. 2020

IEEE Access

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Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxidenitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current (Ioff). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the Ioff caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

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Section: Introductionmentioning

confidence: 99%

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Yan

et al. 2020

IEEE Access

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Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

2022

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SRAM cells are widely used to design memory blocks of, e.g., caches, register files, and translation lookaside buffers. Depending on the SRAM application, the design requirements are different. For instance, in space applications, alongside energy efficiency, reliability is a main issue since the system is launched into space with a limited energy budget and stay exposed to high doses of radiation strikes for a long time. The Nwise cell has recently been proposed by the authors of this paper as the first highly reliable radiation hardened SRAM cell designed with 28nm FD-SOI. In this paper, inspired from the Nwise cell, we introduce another highly reliable radiation hardened SRAM cell, the Pwise cell, which is also designed with 28nm FD-SOI technology. Through comprehensive simulations of state-of-the-art cells, we show that both the Nwise and Pwise cells are competitive radiation hardened SRAMs to use in different memory blocks for space applications: (1) Both have the highest level of Single Event Upsets (SEU) tolerance capability for the temperature range deployed in space applications; further, both have the highest level of the tolerance capability to Multi Event Upsets (MEU). ( 2) Compared with the simulated cells that have comparable tolerance capability, the Nwise cell has low read delay and read power consumption, hence, it can be a good choice for space application cache designs, while the Pwise cell can be a proper candidate for space application register file designs since it has low write and read delay.

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Total dose effects of 28nm FD-SOI CMOS transistors

Cited by 2 publications

References 9 publications

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements

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