Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors

Grot, Boris; Keckler, Stephen W.; Mutlu, Onur

doi:10.1007/978-3-642-24322-6_28

Cited by 7 publications

(9 citation statements)

References 23 publications

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“…These approaches for the most part attempt to limit the rates of each flow [12,13,19,14]. However, quality-of-service guarantees are known to be not sufficient for timing channel protection [37].…”

Section: Related Workmentioning

confidence: 99%

“…While QoS can minimize the performance impact of sharing between domains by providing a minimum guaranteed level of service for each domain (or class) [12,13,19,14], as shown by Wang and Suh, quality of service techniques will still allow timing variations and thus do not truly support noninterference [37]. The only way to be certain that the domains are non-interfering is to statically schedule the domains on the network over time.…”

Section: Introductionmentioning

confidence: 99%

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SurfNoC

Wassel

Gao

Oberg

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

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As multicore processors find increasing adoption in domains such as aerospace and medical devices where failures have the potential to be catastrophic, strong performance isolation and security become first-class design constraints. When cores are used to run separate pieces of the system, strong time and space partitioning can help provide such guarantees. However, as the number of partitions or the asymmetry in partition bandwidth allocations grows, the additional latency incurred by time multiplexing the network can significantly impact performance.In this paper, we introduce SurfNoC, an on-chip network that significantly reduces the latency incurred by temporal partitioning. By carefully scheduling the network into waves that flow across the interconnect, data from different domains carried by these waves are strictly non-interfering while avoiding the significant overheads associated with cycleby-cycle time multiplexing. We describe the scheduling policy and router microarchitecture changes required, and evaluate the information-flow security of a synthesizable implementation through gate-level information flow analysis. When comparing our approach for varying numbers of domains and network sizes, we find that in many cases SurfNoC can reduce the latency overhead of implementing cycle-level non-interference by up to 85%.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

SurfNoC

Wassel

Gao

Oberg

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

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“…MeshX4 produces the highest network throughput, benefiting from its multi-network design. However, MeshX4 increases the complexity of the crossbar, which incurs a big area overhead [11]. Next, we investigate the performance of an APCR router in recently proposed topologies, as shown in Figure 11 (b).…”

Section: Topology Studiesmentioning

confidence: 99%

Apcr

Wang

Kumar

Yum

et al. 2012

Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques

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Chip Multi-Processor (CMP) architectures have become mainstream for designing processors. With a large number of cores, Network-On-Chip (NOC) provides a scalable communication method for CMP architectures, where wires become abundant resources available inside the chip. NOC must be carefully designed to meet constraints of power and area, and provide ultra low latencies. In this paper, we propose an Adaptive Physical Channel Regulator (APCR) for NOC routers to exploit huge wiring resources. The flit size in an APCR router is less than the physical channel width (phit size) to provide finer granularity flow control. An APCR router allows flits from different packets or flows to share the same physical channel in a single cycle. The three regulation schemes (Monopolizing, Fair-sharing and Channel-stealing) intelligently allocate the output channel resources considering not only the availability of physical channels but the occupancy of input buffers. In an APCR router, each Virtual Channel can forward a dynamic number of flits every cycle depending on the run-time network status. Our simulation results using a detailed cycle-accurate simulator show that an APCR router improves the network throughput by over 100% in synthetic workloads, compared with a traditional design with the same buffer size. An APCR router can outperform a traditional router even if the buffer size is halved.

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“…4,5 One approach to these problems is a technique that can verify noninterference of hardware/software systems (including high-performance features such as pipelining and caching) using gate-level information flow tracking. [6][7][8] More recently, researchers proposed a NoC timing-channel protection scheme for a system with security lattices.…”

Section: Timing Channels and Noninterference In Microarchitecturementioning

confidence: 99%

“…Although QoS can minimize the performance impact of sharing between domains by providing a minimum guaranteed level of service for each domain (or class), [2][3][4][5] as Wang and Suh show, QoS techniques still allow some degree of timing variations and thus do not truly support noninterference. 1 The only way to be certain that the domains are noninterfering is to statically schedule them on the network over time.…”

mentioning

confidence: 99%